1/*
2 * Copyright (c) 2010-2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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450 // reset the bit corresponding to this address in the snoop filter
451 // below.
452 allocateWriteBuffer(wbPkt, forward_time);
453 }
454 writebacks.pop_front();
455 }
456}
457
458
459void
460Cache::recvTimingSnoopResp(PacketPtr pkt)
461{
462 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
463 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
464
465 assert(pkt->isResponse());
466

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948 // access in timing mode
949
950 CacheBlk *blk = NULL;
951 PacketList writebacks;
952 bool satisfied = access(pkt, blk, lat, writebacks);
953
954 // handle writebacks resulting from the access here to ensure they
955 // logically proceed anything happening below
956 while (!writebacks.empty()){
957 PacketPtr wbPkt = writebacks.front();
958 memSidePort->sendAtomic(wbPkt);
959 writebacks.pop_front();
960 delete wbPkt;
961 }
962
963 if (!satisfied) {
964 // MISS
965
966 PacketPtr bus_pkt = getBusPacket(pkt, blk, pkt->needsExclusive());
967
968 bool is_forward = (bus_pkt == NULL);
969

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1035 // to pollute the cache in atomic mode since there is no bandwidth
1036 // contention. If we ever do want to enable prefetching in atomic
1037 // mode, though, this is the place to do it... see timingAccess()
1038 // for an example (though we'd want to issue the prefetch(es)
1039 // immediately rather than calling requestMemSideBus() as we do
1040 // there).
1041
1042 // Handle writebacks (from the response handling) if needed
1043 while (!writebacks.empty()){
1044 PacketPtr wbPkt = writebacks.front();
1045 memSidePort->sendAtomic(wbPkt);
1046 writebacks.pop_front();
1047 delete wbPkt;
1048 }
1049
1050 if (pkt->needsResponse()) {
1051 pkt->makeAtomicResponse();
1052 }
1053
1054 return lat * clockPeriod();
1055}
1056

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1901Cache::recvTimingSnoopReq(PacketPtr pkt)
1902{
1903 DPRINTF(Cache, "%s for %s addr %#llx size %d\n", __func__,
1904 pkt->cmdString(), pkt->getAddr(), pkt->getSize());
1905
1906 // Snoops shouldn't happen when bypassing caches
1907 assert(!system->bypassCaches());
1908
1909 // no need to snoop writebacks or requests that are not in range
1910 if (!inRange(pkt->getAddr())) {
1911 return;
1912 }
1913
1914 bool is_secure = pkt->isSecure();
1915 CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure);
1916
1917 Addr blk_addr = blockAlign(pkt->getAddr());

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2039}
2040
2041Tick
2042Cache::recvAtomicSnoop(PacketPtr pkt)
2043{
2044 // Snoops shouldn't happen when bypassing caches
2045 assert(!system->bypassCaches());
2046
2047 // no need to snoop writebacks or requests that are not in range. In
2048 // atomic we have no Writebacks/CleanEvicts queued and no prefetches,
2049 // hence there is no need to snoop upwards and determine if they are
2050 // present above.
2051 if (pkt->evictingBlock() || !inRange(pkt->getAddr())) {
2052 return 0;
2053 }
2054
2055 CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure());
2056 uint32_t snoop_delay = handleSnoop(pkt, blk, false, false, false);
2057 return snoop_delay + lookupLatency * clockPeriod();
2058}
2059

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2139 }
2140 }
2141 }
2142
2143 return NULL;
2144}
2145
2146bool
2147Cache::isCachedAbove(const PacketPtr pkt) const
2148{
2149 if (!forwardSnoops)
2150 return false;
2151 // Mirroring the flow of HardPFReqs, the cache sends CleanEvict and
2152 // Writeback snoops into upper level caches to check for copies of the
2153 // same block. Using the BLOCK_CACHED flag with the Writeback/CleanEvict
2154 // packet, the cache can inform the crossbar below of presence or absence
2155 // of the block.
2156
2157 Packet snoop_pkt(pkt, true, false);
2158 snoop_pkt.setExpressSnoop();
2159 // Assert that packet is either Writeback or CleanEvict and not a prefetch
2160 // request because prefetch requests need an MSHR and may generate a snoop
2161 // response.
2162 assert(pkt->evictingBlock());
2163 snoop_pkt.senderState = NULL;
2164 cpuSidePort->sendTimingSnoopReq(&snoop_pkt);
2165 // Writeback/CleanEvict snoops do not generate a separate snoop response.
2166 assert(!(snoop_pkt.memInhibitAsserted()));
2167 return snoop_pkt.isBlockCached();
2168}
2169
2170PacketPtr
2171Cache::getTimingPacket()
2172{
2173 MSHR *mshr = getNextMSHR();
2174
2175 if (mshr == NULL) {

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