base.hh (9486:569e1f1d762d) base.hh (9529:28d6d9663a7e)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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257 * tries to capture this latency.
258 */
259 const Cycles responseLatency;
260
261 /** The number of targets for each MSHR. */
262 const int numTarget;
263
264 /** Do we forward snoops from mem side port through to cpu side port? */
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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257 * tries to capture this latency.
258 */
259 const Cycles responseLatency;
260
261 /** The number of targets for each MSHR. */
262 const int numTarget;
263
264 /** Do we forward snoops from mem side port through to cpu side port? */
265 bool forwardSnoops;
265 const bool forwardSnoops;
266
267 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
268 * never try to forward ownership and similar optimizations to the cpu
269 * side */
266
267 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
268 * never try to forward ownership and similar optimizations to the cpu
269 * side */
270 bool isTopLevel;
270 const bool isTopLevel;
271
272 /**
273 * Bit vector of the blocking reasons for the access path.
274 * @sa #BlockedCause
275 */
276 uint8_t blocked;
277
278 /** Increasing order number assigned to each incoming request. */

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285 MSHR *noTargetMSHR;
286
287 /** The number of misses to trigger an exit event. */
288 Counter missCount;
289
290 /**
291 * The address range to which the cache responds on the CPU side.
292 * Normally this is all possible memory addresses. */
271
272 /**
273 * Bit vector of the blocking reasons for the access path.
274 * @sa #BlockedCause
275 */
276 uint8_t blocked;
277
278 /** Increasing order number assigned to each incoming request. */

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285 MSHR *noTargetMSHR;
286
287 /** The number of misses to trigger an exit event. */
288 Counter missCount;
289
290 /**
291 * The address range to which the cache responds on the CPU side.
292 * Normally this is all possible memory addresses. */
293 AddrRangeList addrRanges;
293 const AddrRangeList addrRanges;
294
295 public:
296 /** System we are currently operating in. */
297 System *system;
298
299 // Statistics
300 /**
301 * @addtogroup CacheStatistics

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490 return allocateBufferInternal(&mshrQueue,
491 pkt->getAddr(), pkt->getSize(),
492 pkt, time, requestBus);
493 }
494
495 /**
496 * Returns true if the cache is blocked for accesses.
497 */
294
295 public:
296 /** System we are currently operating in. */
297 System *system;
298
299 // Statistics
300 /**
301 * @addtogroup CacheStatistics

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490 return allocateBufferInternal(&mshrQueue,
491 pkt->getAddr(), pkt->getSize(),
492 pkt, time, requestBus);
493 }
494
495 /**
496 * Returns true if the cache is blocked for accesses.
497 */
498 bool isBlocked()
498 bool isBlocked() const
499 {
500 return blocked != 0;
501 }
502
503 /**
504 * Marks the access path of the cache as blocked for the given cause. This
505 * also sets the blocked flag in the slave interface.
506 * @param cause The reason for the cache blocking.

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555 // we can't deassert them. Leaving this in as a no-op since
556 // the prefetcher calls it to indicate that it no longer wants
557 // to request a prefetch, and someday that might be
558 // interesting again.
559 }
560
561 virtual unsigned int drain(DrainManager *dm);
562
499 {
500 return blocked != 0;
501 }
502
503 /**
504 * Marks the access path of the cache as blocked for the given cause. This
505 * also sets the blocked flag in the slave interface.
506 * @param cause The reason for the cache blocking.

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555 // we can't deassert them. Leaving this in as a no-op since
556 // the prefetcher calls it to indicate that it no longer wants
557 // to request a prefetch, and someday that might be
558 // interesting again.
559 }
560
561 virtual unsigned int drain(DrainManager *dm);
562
563 virtual bool inCache(Addr addr) = 0;
563 virtual bool inCache(Addr addr) const = 0;
564
564
565 virtual bool inMissQueue(Addr addr) = 0;
565 virtual bool inMissQueue(Addr addr) const = 0;
566
567 void incMissCount(PacketPtr pkt)
568 {
569 assert(pkt->req->masterId() < system->maxMasters());
570 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
571
572 if (missCount) {
573 --missCount;

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567 void incMissCount(PacketPtr pkt)
568 {
569 assert(pkt->req->masterId() < system->maxMasters());
570 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
571
572 if (missCount) {
573 --missCount;

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