base.hh (9163:3b5e13ac1940) base.hh (9263:066099902102)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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224 }
225
226 /** Block size of this cache */
227 const unsigned blkSize;
228
229 /**
230 * The latency of a hit in this device.
231 */
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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224 }
225
226 /** Block size of this cache */
227 const unsigned blkSize;
228
229 /**
230 * The latency of a hit in this device.
231 */
232 int hitLatency;
232 const Tick hitLatency;
233
233
234 /**
235 * The latency of sending reponse to its upper level cache/core on a
236 * linefill. In most contemporary processors, the return path on a cache
237 * miss is much quicker that the hit latency. The responseLatency parameter
238 * tries to capture this latency.
239 */
240 const Tick responseLatency;
241
234 /** The number of targets for each MSHR. */
235 const int numTarget;
236
237 /** Do we forward snoops from mem side port through to cpu side port? */
238 bool forwardSnoops;
239
240 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
241 * never try to forward ownership and similar optimizations to the cpu

--- 320 unchanged lines hidden --- 		242 /** The number of targets for each MSHR. */
243 const int numTarget;
244
245 /** Do we forward snoops from mem side port through to cpu side port? */
246 bool forwardSnoops;
247
248 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
249 * never try to forward ownership and similar optimizations to the cpu

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