base.hh (8883:c92153af04ac) base.hh (8914:8c3bd7bea667)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
67#include "mem/request.hh"
68#include "mem/request.hh"
68#include "mem/tport.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**

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113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**

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113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public SimpleTimingPort
121 class CacheMasterPort : public QueuedPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 schedSendEvent(time);
134 queue.schedSendEvent(time);
135 }
136
135 }
136
137 /**
138 * Schedule the transmissions of a response packet at a given
139 * point in time.
140 *
141 * @param pkt response packet
142 * @param when time to send the response
143 */
137 void respond(PacketPtr pkt, Tick time) {
144 void respond(PacketPtr pkt, Tick time) {
138 schedSendTiming(pkt, time);
145 queue.schedSendTiming(pkt, time);
139 }
140
141 protected:
142
143 CacheMasterPort(const std::string &_name, BaseCache *_cache,
146 }
147
148 protected:
149
150 CacheMasterPort(const std::string &_name, BaseCache *_cache,
144 const std::string &_label);
151 PacketQueue &_queue) :
152 QueuedPort(_name, _cache, _queue)
153 { }
145
146 /**
147 * Memory-side port always snoops.
148 *
154
155 /**
156 * Memory-side port always snoops.
157 *
149 * return always true
158 * @return always true
150 */
151 virtual bool isSnooping() { return true; }
152 };
153
154 /**
155 * A cache slave port is used for the CPU-side port of the cache,
156 * and it is basically a simple timing port that uses a transmit
157 * list for responses to the CPU (or connected master). In
158 * addition, it has the functionality to block the port for
159 * incoming requests. If blocked, the port will issue a retry once
160 * unblocked.
161 */
159 */
160 virtual bool isSnooping() { return true; }
161 };
162
163 /**
164 * A cache slave port is used for the CPU-side port of the cache,
165 * and it is basically a simple timing port that uses a transmit
166 * list for responses to the CPU (or connected master). In
167 * addition, it has the functionality to block the port for
168 * incoming requests. If blocked, the port will issue a retry once
169 * unblocked.
170 */
162 class CacheSlavePort : public SimpleTimingPort
171 class CacheSlavePort : public QueuedPort
163 {
164
165 public:
166
167 /** Do not accept any new requests. */
168 void setBlocked();
169
170 /** Return to normal operation and accept new requests. */
171 void clearBlocked();
172
172 {
173
174 public:
175
176 /** Do not accept any new requests. */
177 void setBlocked();
178
179 /** Return to normal operation and accept new requests. */
180 void clearBlocked();
181
182 /**
183 * Schedule the transmissions of a response packet at a given
184 * point in time.
185 *
186 * @param pkt response packet
187 * @param when time to send the response
188 */
173 void respond(PacketPtr pkt, Tick time) {
189 void respond(PacketPtr pkt, Tick time) {
174 schedSendTiming(pkt, time);
190 queue.schedSendTiming(pkt, time);
175 }
176
177 protected:
178
179 CacheSlavePort(const std::string &_name, BaseCache *_cache,
180 const std::string &_label);
181
191 }
192
193 protected:
194
195 CacheSlavePort(const std::string &_name, BaseCache *_cache,
196 const std::string &_label);
197
198 /** A normal packet queue used to store responses. */
199 PacketQueue queue;
200
182 bool blocked;
183
184 bool mustSendRetry;
185
186 private:
187
188 EventWrapper<Port, &Port::sendRetry> sendRetryEvent;
189

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202
203 bool mustSendRetry;
204
205 private:
206
207 EventWrapper<Port, &Port::sendRetry> sendRetryEvent;
208

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