| base.hh (8856:241ee47b0dc6) | base.hh (8883:c92153af04ac) |
|---|---|
| 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 255 unchanged lines hidden (view full) --- 264 Counter missCount; 265 266 /** The drain event. */ 267 Event *drainEvent; 268 269 /** 270 * The address range to which the cache responds on the CPU side. 271 * Normally this is all possible memory addresses. */ | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 255 unchanged lines hidden (view full) --- 264 Counter missCount; 265 266 /** The drain event. */ 267 Event *drainEvent; 268 269 /** 270 * The address range to which the cache responds on the CPU side. 271 * Normally this is all possible memory addresses. */ |
| 272 Range<Addr> addrRange; | 272 AddrRangeList addrRanges; |
| 273 274 public: 275 /** System we are currently operating in. */ 276 System *system; 277 278 // Statistics 279 /** 280 * @addtogroup CacheStatistics --- 153 unchanged lines hidden (view full) --- 434 { 435 return blkSize; 436 } 437 438 439 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 440 441 | 273 274 public: 275 /** System we are currently operating in. */ 276 System *system; 277 278 // Statistics 279 /** 280 * @addtogroup CacheStatistics --- 153 unchanged lines hidden (view full) --- 434 { 435 return blkSize; 436 } 437 438 439 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 440 441 |
| 442 const Range<Addr> &getAddrRange() const { return addrRange; } | 442 const AddrRangeList &getAddrRanges() const { return addrRanges; } |
| 443 444 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 445 { 446 assert(!pkt->req->isUncacheable()); 447 return allocateBufferInternal(&mshrQueue, 448 blockAlign(pkt->getAddr()), blkSize, 449 pkt, time, requestBus); 450 } --- 111 unchanged lines hidden --- | 443 444 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 445 { 446 assert(!pkt->req->isUncacheable()); 447 return allocateBufferInternal(&mshrQueue, 448 blockAlign(pkt->getAddr()), blkSize, 449 pkt, time, requestBus); 450 } --- 111 unchanged lines hidden --- |