base.hh (8809:bb10807da889) base.hh (8833:2870638642bd)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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53#include "mem/mem_object.hh"
54#include "mem/packet.hh"
55#include "mem/request.hh"
56#include "mem/tport.hh"
57#include "params/BaseCache.hh"
58#include "sim/eventq.hh"
59#include "sim/full_system.hh"
60#include "sim/sim_exit.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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53#include "mem/mem_object.hh"
54#include "mem/packet.hh"
55#include "mem/request.hh"
56#include "mem/tport.hh"
57#include "params/BaseCache.hh"
58#include "sim/eventq.hh"
59#include "sim/full_system.hh"
60#include "sim/sim_exit.hh"
61#include "sim/system.hh"
61
62class MSHR;
63/**
64 * A basic cache interface. Implements some common functions for speed.
65 */
66class BaseCache : public MemObject
67{
68 /**

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215 /** The drain event. */
216 Event *drainEvent;
217
218 /**
219 * The address range to which the cache responds on the CPU side.
220 * Normally this is all possible memory addresses. */
221 Range<Addr> addrRange;
222
62
63class MSHR;
64/**
65 * A basic cache interface. Implements some common functions for speed.
66 */
67class BaseCache : public MemObject
68{
69 /**

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216 /** The drain event. */
217 Event *drainEvent;
218
219 /**
220 * The address range to which the cache responds on the CPU side.
221 * Normally this is all possible memory addresses. */
222 Range<Addr> addrRange;
223
223 /** number of cpus sharing this cache - from config file */
224 int _numCpus;
225
226 public:
224 public:
227 int numCpus() { return _numCpus; }
225 /** System we are currently operating in. */
226 System *system;
227
228 // Statistics
229 /**
230 * @addtogroup CacheStatistics
231 * @{
232 */
233
234 /** Number of hits per thread for each type of command. @sa Packet::Command */
235 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];

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483 }
484
485 virtual unsigned int drain(Event *de);
486
487 virtual bool inCache(Addr addr) = 0;
488
489 virtual bool inMissQueue(Addr addr) = 0;
490
228 // Statistics
229 /**
230 * @addtogroup CacheStatistics
231 * @{
232 */
233
234 /** Number of hits per thread for each type of command. @sa Packet::Command */
235 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];

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483 }
484
485 virtual unsigned int drain(Event *de);
486
487 virtual bool inCache(Addr addr) = 0;
488
489 virtual bool inMissQueue(Addr addr) = 0;
490
491 void incMissCount(PacketPtr pkt, int id)
491 void incMissCount(PacketPtr pkt)
492 {
492 {
493 assert(pkt->req->masterId() < system->maxMasters());
494 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
493
495
494 if (pkt->cmd == MemCmd::Writeback) {
495 assert(id == -1);
496 misses[pkt->cmdToIndex()][0]++;
497 /* same thing for writeback hits as misses - no context id
498 * available, meanwhile writeback hit/miss stats are not used
499 * in any aggregate hit/miss calculations, so just lump them all
500 * in bucket 0 */
501 } else if (FullSystem && id == -1) {
502 // Device accesses have id -1
503 // lump device accesses into their own bucket
504 misses[pkt->cmdToIndex()][_numCpus]++;
505 } else {
506 misses[pkt->cmdToIndex()][id % _numCpus]++;
507 }
508
509 if (missCount) {
510 --missCount;
511 if (missCount == 0)
512 exitSimLoop("A cache reached the maximum miss count");
513 }
514 }
496 if (missCount) {
497 --missCount;
498 if (missCount == 0)
499 exitSimLoop("A cache reached the maximum miss count");
500 }
501 }
515 void incHitCount(PacketPtr pkt, int id)
502 void incHitCount(PacketPtr pkt)
516 {
503 {
504 assert(pkt->req->masterId() < system->maxMasters());
505 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
517
506
518 /* Writeback requests don't have a context id associated with
519 * them, so attributing a hit to a -1 context id is obviously a
520 * problem. I've noticed in the stats that hits are split into
521 * demand and non-demand hits - neither of which include writeback
522 * hits, so here, I'll just put the writeback hits into bucket 0
523 * since it won't mess with any other stats -hsul */
524 if (pkt->cmd == MemCmd::Writeback) {
525 assert(id == -1);
526 hits[pkt->cmdToIndex()][0]++;
527 } else if (FullSystem && id == -1) {
528 // Device accesses have id -1
529 // lump device accesses into their own bucket
530 hits[pkt->cmdToIndex()][_numCpus]++;
531 } else {
532 /* the % is necessary in case there are switch cpus */
533 hits[pkt->cmdToIndex()][id % _numCpus]++;
534 }
535 }
536
537};
538
539#endif //__BASE_CACHE_HH__
507 }
508
509};
510
511#endif //__BASE_CACHE_HH__