base.hh (8737:770ccf3af571) base.hh (8786:8be24baf68b8)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52#include "debug/CachePort.hh"
53#include "mem/cache/mshr_queue.hh"
54#include "mem/mem_object.hh"
55#include "mem/packet.hh"
56#include "mem/request.hh"
57#include "mem/tport.hh"
58#include "params/BaseCache.hh"
59#include "sim/eventq.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52#include "debug/CachePort.hh"
53#include "mem/cache/mshr_queue.hh"
54#include "mem/mem_object.hh"
55#include "mem/packet.hh"
56#include "mem/request.hh"
57#include "mem/tport.hh"
58#include "params/BaseCache.hh"
59#include "sim/eventq.hh"
60#include "sim/full_system.hh"
60#include "sim/sim_exit.hh"
61
62class MSHR;
63/**
64 * A basic cache interface. Implements some common functions for speed.
65 */
66class BaseCache : public MemObject
67{
68 /**
69 * Indexes to enumerate the MSHR queues.
70 */
71 enum MSHRQueueIndex {
72 MSHRQueue_MSHRs,
73 MSHRQueue_WriteBuffer
74 };
75
61#include "sim/sim_exit.hh"
62
63class MSHR;
64/**
65 * A basic cache interface. Implements some common functions for speed.
66 */
67class BaseCache : public MemObject
68{
69 /**
70 * Indexes to enumerate the MSHR queues.
71 */
72 enum MSHRQueueIndex {
73 MSHRQueue_MSHRs,
74 MSHRQueue_WriteBuffer
75 };
76
76 public:
77 /**
78 * Reasons for caches to be blocked.
79 */
80 enum BlockedCause {
81 Blocked_NoMSHRs = MSHRQueue_MSHRs,
82 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
83 Blocked_NoTargets,
84 NUM_BLOCKED_CAUSES
85 };
86
77 /**
78 * Reasons for caches to be blocked.
79 */
80 enum BlockedCause {
81 Blocked_NoMSHRs = MSHRQueue_MSHRs,
82 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
83 Blocked_NoTargets,
84 NUM_BLOCKED_CAUSES
85 };
86
87 public:
87 /**
88 * Reasons for cache to request a bus.
89 */
90 enum RequestCause {
91 Request_MSHR = MSHRQueue_MSHRs,
92 Request_WB = MSHRQueue_WriteBuffer,
93 Request_PF,
94 NUM_REQUEST_CAUSES
95 };
96
88 /**
89 * Reasons for cache to request a bus.
90 */
91 enum RequestCause {
92 Request_MSHR = MSHRQueue_MSHRs,
93 Request_WB = MSHRQueue_WriteBuffer,
94 Request_PF,
95 NUM_REQUEST_CAUSES
96 };
97
97 protected:
98 private:
98
99 class CachePort : public SimpleTimingPort
100 {
101 public:
102 BaseCache *cache;
103
104 protected:
105 CachePort(const std::string &_name, BaseCache *_cache,
106 const std::string &_label);
107
99
100 class CachePort : public SimpleTimingPort
101 {
102 public:
103 BaseCache *cache;
104
105 protected:
106 CachePort(const std::string &_name, BaseCache *_cache,
107 const std::string &_label);
108
109 virtual void recvStatusChange(Status status);
110
108 virtual unsigned deviceBlockSize() const;
109
110 bool recvRetryCommon();
111
112 typedef EventWrapper<Port, &Port::sendRetry>
113 SendRetryEvent;
114
115 const std::string label;
116
117 public:
111 virtual unsigned deviceBlockSize() const;
112
113 bool recvRetryCommon();
114
115 typedef EventWrapper<Port, &Port::sendRetry>
116 SendRetryEvent;
117
118 const std::string label;
119
120 public:
121 void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; }
122
118 void setBlocked();
119
120 void clearBlocked();
121
122 bool checkFunctional(PacketPtr pkt);
123
123 void setBlocked();
124
125 void clearBlocked();
126
127 bool checkFunctional(PacketPtr pkt);
128
129 CachePort *otherPort;
130
124 bool blocked;
125
126 bool mustSendRetry;
127
128 void requestBus(RequestCause cause, Tick time)
129 {
130 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
131 if (!waitingOnRetry) {
132 schedSendEvent(time);
133 }
134 }
135
136 void respond(PacketPtr pkt, Tick time) {
137 schedSendTiming(pkt, time);
138 }
139 };
140
131 bool blocked;
132
133 bool mustSendRetry;
134
135 void requestBus(RequestCause cause, Tick time)
136 {
137 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
138 if (!waitingOnRetry) {
139 schedSendEvent(time);
140 }
141 }
142
143 void respond(PacketPtr pkt, Tick time) {
144 schedSendTiming(pkt, time);
145 }
146 };
147
148 public: //Made public so coherence can get at it.
141 CachePort *cpuSidePort;
142 CachePort *memSidePort;
143
144 protected:
145
146 /** Miss status registers */
147 MSHRQueue mshrQueue;
148

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493
494 if (pkt->cmd == MemCmd::Writeback) {
495 assert(id == -1);
496 misses[pkt->cmdToIndex()][0]++;
497 /* same thing for writeback hits as misses - no context id
498 * available, meanwhile writeback hit/miss stats are not used
499 * in any aggregate hit/miss calculations, so just lump them all
500 * in bucket 0 */
149 CachePort *cpuSidePort;
150 CachePort *memSidePort;
151
152 protected:
153
154 /** Miss status registers */
155 MSHRQueue mshrQueue;
156

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501
502 if (pkt->cmd == MemCmd::Writeback) {
503 assert(id == -1);
504 misses[pkt->cmdToIndex()][0]++;
505 /* same thing for writeback hits as misses - no context id
506 * available, meanwhile writeback hit/miss stats are not used
507 * in any aggregate hit/miss calculations, so just lump them all
508 * in bucket 0 */
501#if FULL_SYSTEM
502 } else if (id == -1) {
509 } else if (FullSystem && id == -1) {
503 // Device accesses have id -1
504 // lump device accesses into their own bucket
505 misses[pkt->cmdToIndex()][_numCpus]++;
510 // Device accesses have id -1
511 // lump device accesses into their own bucket
512 misses[pkt->cmdToIndex()][_numCpus]++;
506#endif
507 } else {
508 misses[pkt->cmdToIndex()][id % _numCpus]++;
509 }
510
511 if (missCount) {
512 --missCount;
513 if (missCount == 0)
514 exitSimLoop("A cache reached the maximum miss count");

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521 * them, so attributing a hit to a -1 context id is obviously a
522 * problem. I've noticed in the stats that hits are split into
523 * demand and non-demand hits - neither of which include writeback
524 * hits, so here, I'll just put the writeback hits into bucket 0
525 * since it won't mess with any other stats -hsul */
526 if (pkt->cmd == MemCmd::Writeback) {
527 assert(id == -1);
528 hits[pkt->cmdToIndex()][0]++;
513 } else {
514 misses[pkt->cmdToIndex()][id % _numCpus]++;
515 }
516
517 if (missCount) {
518 --missCount;
519 if (missCount == 0)
520 exitSimLoop("A cache reached the maximum miss count");

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527 * them, so attributing a hit to a -1 context id is obviously a
528 * problem. I've noticed in the stats that hits are split into
529 * demand and non-demand hits - neither of which include writeback
530 * hits, so here, I'll just put the writeback hits into bucket 0
531 * since it won't mess with any other stats -hsul */
532 if (pkt->cmd == MemCmd::Writeback) {
533 assert(id == -1);
534 hits[pkt->cmdToIndex()][0]++;
529#if FULL_SYSTEM
530 } else if (id == -1) {
535 } else if (FullSystem && id == -1) {
531 // Device accesses have id -1
532 // lump device accesses into their own bucket
533 hits[pkt->cmdToIndex()][_numCpus]++;
536 // Device accesses have id -1
537 // lump device accesses into their own bucket
538 hits[pkt->cmdToIndex()][_numCpus]++;
534#endif
535 } else {
536 /* the % is necessary in case there are switch cpus */
537 hits[pkt->cmdToIndex()][id % _numCpus]++;
538 }
539 }
540
541};
542
543#endif //__BASE_CACHE_HH__
539 } else {
540 /* the % is necessary in case there are switch cpus */
541 hits[pkt->cmdToIndex()][id % _numCpus]++;
542 }
543 }
544
545};
546
547#endif //__BASE_CACHE_HH__