base.hh (7823:dac01f14f20f) base.hh (8134:b01a51ff05fa)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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189 int hitLatency;
190
191 /** The number of targets for each MSHR. */
192 const int numTarget;
193
194 /** Do we forward snoops from mem side port through to cpu side port? */
195 bool forwardSnoops;
196
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 180 unchanged lines hidden (view full) ---

189 int hitLatency;
190
191 /** The number of targets for each MSHR. */
192 const int numTarget;
193
194 /** Do we forward snoops from mem side port through to cpu side port? */
195 bool forwardSnoops;
196
197 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
198 * never try to forward ownership and similar optimizations to the cpu
199 * side */
200 bool isTopLevel;
201
197 /**
198 * Bit vector of the blocking reasons for the access path.
199 * @sa #BlockedCause
200 */
201 uint8_t blocked;
202
203 /** Increasing order number assigned to each incoming request. */
204 uint64_t order;

--- 339 unchanged lines hidden --- 		202 /**
203 * Bit vector of the blocking reasons for the access path.
204 * @sa #BlockedCause
205 */
206 uint8_t blocked;
207
208 /** Increasing order number assigned to each incoming request. */
209 uint64_t order;

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