base.hh (6978:ab05e20dc4a7) | base.hh (7461:5a07045d0af2) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 310 unchanged lines hidden (view full) --- 319 /** Total cycle latency of overall MSHR misses. */ 320 Stats::Formula overallMshrMissLatency; 321 322 /** Total cycle latency of each MSHR miss, per command and thread. */ 323 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 324 /** Total cycle latency of overall MSHR misses. */ 325 Stats::Formula overallMshrUncacheableLatency; 326 | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 310 unchanged lines hidden (view full) --- 319 /** Total cycle latency of overall MSHR misses. */ 320 Stats::Formula overallMshrMissLatency; 321 322 /** Total cycle latency of each MSHR miss, per command and thread. */ 323 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 324 /** Total cycle latency of overall MSHR misses. */ 325 Stats::Formula overallMshrUncacheableLatency; 326 |
327#if 0 |
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327 /** The total number of MSHR accesses per command and thread. */ 328 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 329 /** The total number of demand MSHR accesses. */ 330 Stats::Formula demandMshrAccesses; 331 /** The total number of MSHR accesses. */ 332 Stats::Formula overallMshrAccesses; | 328 /** The total number of MSHR accesses per command and thread. */ 329 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 330 /** The total number of demand MSHR accesses. */ 331 Stats::Formula demandMshrAccesses; 332 /** The total number of MSHR accesses. */ 333 Stats::Formula overallMshrAccesses; |
334#endif |
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333 334 /** The miss rate in the MSHRs pre command and thread. */ 335 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 336 /** The demand miss rate in the MSHRs. */ 337 Stats::Formula demandMshrMissRate; 338 /** The overall miss rate in the MSHRs. */ 339 Stats::Formula overallMshrMissRate; 340 --- 201 unchanged lines hidden --- | 335 336 /** The miss rate in the MSHRs pre command and thread. */ 337 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 338 /** The demand miss rate in the MSHRs. */ 339 Stats::Formula demandMshrMissRate; 340 /** The overall miss rate in the MSHRs. */ 341 Stats::Formula overallMshrMissRate; 342 --- 201 unchanged lines hidden --- |