base.hh (6666:3199397fd905) base.hh (6978:ab05e20dc4a7)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 33 unchanged lines hidden (view full) ---

42#include <string>
43#include <list>
44#include <algorithm>
45
46#include "base/misc.hh"
47#include "base/statistics.hh"
48#include "base/trace.hh"
49#include "base/types.hh"
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 33 unchanged lines hidden (view full) ---

42#include <string>
43#include <list>
44#include <algorithm>
45
46#include "base/misc.hh"
47#include "base/statistics.hh"
48#include "base/trace.hh"
49#include "base/types.hh"
50#include "config/full_system.hh"
50#include "mem/cache/mshr_queue.hh"
51#include "mem/mem_object.hh"
52#include "mem/packet.hh"
53#include "mem/tport.hh"
54#include "mem/request.hh"
55#include "params/BaseCache.hh"
56#include "sim/eventq.hh"
57#include "sim/sim_exit.hh"

--- 156 unchanged lines hidden (view full) ---

214 /** The drain event. */
215 Event *drainEvent;
216
217 /**
218 * The address range to which the cache responds on the CPU side.
219 * Normally this is all possible memory addresses. */
220 Range<Addr> addrRange;
221
51#include "mem/cache/mshr_queue.hh"
52#include "mem/mem_object.hh"
53#include "mem/packet.hh"
54#include "mem/tport.hh"
55#include "mem/request.hh"
56#include "params/BaseCache.hh"
57#include "sim/eventq.hh"
58#include "sim/sim_exit.hh"

--- 156 unchanged lines hidden (view full) ---

215 /** The drain event. */
216 Event *drainEvent;
217
218 /**
219 * The address range to which the cache responds on the CPU side.
220 * Normally this is all possible memory addresses. */
221 Range<Addr> addrRange;
222
223 /** number of cpus sharing this cache - from config file */
224 int _numCpus;
225
222 public:
226 public:
227 int numCpus() { return _numCpus; }
223 // Statistics
224 /**
225 * @addtogroup CacheStatistics
226 * @{
227 */
228
229 /** Number of hits per thread for each type of command. @sa Packet::Command */
230 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];

--- 245 unchanged lines hidden (view full) ---

476 }
477
478 virtual unsigned int drain(Event *de);
479
480 virtual bool inCache(Addr addr) = 0;
481
482 virtual bool inMissQueue(Addr addr) = 0;
483
228 // Statistics
229 /**
230 * @addtogroup CacheStatistics
231 * @{
232 */
233
234 /** Number of hits per thread for each type of command. @sa Packet::Command */
235 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];

--- 245 unchanged lines hidden (view full) ---

481 }
482
483 virtual unsigned int drain(Event *de);
484
485 virtual bool inCache(Addr addr) = 0;
486
487 virtual bool inMissQueue(Addr addr) = 0;
488
484 void incMissCount(PacketPtr pkt)
489 void incMissCount(PacketPtr pkt, int id)
485 {
490 {
486 misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
487
491
492 if (pkt->cmd == MemCmd::Writeback) {
493 assert(id == -1);
494 misses[pkt->cmdToIndex()][0]++;
495 /* same thing for writeback hits as misses - no context id
496 * available, meanwhile writeback hit/miss stats are not used
497 * in any aggregate hit/miss calculations, so just lump them all
498 * in bucket 0 */
499#if FULL_SYSTEM
500 } else if (id == -1) {
501 // Device accesses have id -1
502 // lump device accesses into their own bucket
503 misses[pkt->cmdToIndex()][_numCpus]++;
504#endif
505 } else {
506 misses[pkt->cmdToIndex()][id % _numCpus]++;
507 }
508
488 if (missCount) {
489 --missCount;
490 if (missCount == 0)
491 exitSimLoop("A cache reached the maximum miss count");
492 }
493 }
509 if (missCount) {
510 --missCount;
511 if (missCount == 0)
512 exitSimLoop("A cache reached the maximum miss count");
513 }
514 }
515 void incHitCount(PacketPtr pkt, int id)
516 {
494
517
518 /* Writeback requests don't have a context id associated with
519 * them, so attributing a hit to a -1 context id is obviously a
520 * problem. I've noticed in the stats that hits are split into
521 * demand and non-demand hits - neither of which include writeback
522 * hits, so here, I'll just put the writeback hits into bucket 0
523 * since it won't mess with any other stats -hsul */
524 if (pkt->cmd == MemCmd::Writeback) {
525 assert(id == -1);
526 hits[pkt->cmdToIndex()][0]++;
527#if FULL_SYSTEM
528 } else if (id == -1) {
529 // Device accesses have id -1
530 // lump device accesses into their own bucket
531 hits[pkt->cmdToIndex()][_numCpus]++;
532#endif
533 } else {
534 /* the % is necessary in case there are switch cpus */
535 hits[pkt->cmdToIndex()][id % _numCpus]++;
536 }
537 }
538
495};
496
497#endif //__BASE_CACHE_HH__
539};
540
541#endif //__BASE_CACHE_HH__