base.hh (5875:d82be3235ab4) base.hh (5999:3cf8e71257e0)
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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218 public:
219 // Statistics
220 /**
221 * @addtogroup CacheStatistics
222 * @{
223 */
224
225 /** Number of hits per thread for each type of command. @sa Packet::Command */
1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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218 public:
219 // Statistics
220 /**
221 * @addtogroup CacheStatistics
222 * @{
223 */
224
225 /** Number of hits per thread for each type of command. @sa Packet::Command */
226 Stats::Vector<> hits[MemCmd::NUM_MEM_CMDS];
226 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
227 /** Number of hits for demand accesses. */
228 Stats::Formula demandHits;
229 /** Number of hit for all accesses. */
230 Stats::Formula overallHits;
231
232 /** Number of misses per thread for each type of command. @sa Packet::Command */
227 /** Number of hits for demand accesses. */
228 Stats::Formula demandHits;
229 /** Number of hit for all accesses. */
230 Stats::Formula overallHits;
231
232 /** Number of misses per thread for each type of command. @sa Packet::Command */
233 Stats::Vector<> misses[MemCmd::NUM_MEM_CMDS];
233 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
234 /** Number of misses for demand accesses. */
235 Stats::Formula demandMisses;
236 /** Number of misses for all accesses. */
237 Stats::Formula overallMisses;
238
239 /**
240 * Total number of cycles per thread/command spent waiting for a miss.
241 * Used to calculate the average miss latency.
242 */
234 /** Number of misses for demand accesses. */
235 Stats::Formula demandMisses;
236 /** Number of misses for all accesses. */
237 Stats::Formula overallMisses;
238
239 /**
240 * Total number of cycles per thread/command spent waiting for a miss.
241 * Used to calculate the average miss latency.
242 */
243 Stats::Vector<> missLatency[MemCmd::NUM_MEM_CMDS];
243 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
244 /** Total number of cycles spent waiting for demand misses. */
245 Stats::Formula demandMissLatency;
246 /** Total number of cycles spent waiting for all misses. */
247 Stats::Formula overallMissLatency;
248
249 /** The number of accesses per command and thread. */
250 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
251 /** The number of demand accesses. */

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263 /** The average miss latency per command and thread. */
264 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
265 /** The average miss latency for demand misses. */
266 Stats::Formula demandAvgMissLatency;
267 /** The average miss latency for all misses. */
268 Stats::Formula overallAvgMissLatency;
269
270 /** The total number of cycles blocked for each blocked cause. */
244 /** Total number of cycles spent waiting for demand misses. */
245 Stats::Formula demandMissLatency;
246 /** Total number of cycles spent waiting for all misses. */
247 Stats::Formula overallMissLatency;
248
249 /** The number of accesses per command and thread. */
250 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
251 /** The number of demand accesses. */

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263 /** The average miss latency per command and thread. */
264 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
265 /** The average miss latency for demand misses. */
266 Stats::Formula demandAvgMissLatency;
267 /** The average miss latency for all misses. */
268 Stats::Formula overallAvgMissLatency;
269
270 /** The total number of cycles blocked for each blocked cause. */
271 Stats::Vector<> blocked_cycles;
271 Stats::Vector blocked_cycles;
272 /** The number of times this cache blocked for each blocked cause. */
272 /** The number of times this cache blocked for each blocked cause. */
273 Stats::Vector<> blocked_causes;
273 Stats::Vector blocked_causes;
274
275 /** The average number of cycles blocked for each blocked cause. */
276 Stats::Formula avg_blocked;
277
278 /** The number of fast writes (WH64) performed. */
274
275 /** The average number of cycles blocked for each blocked cause. */
276 Stats::Formula avg_blocked;
277
278 /** The number of fast writes (WH64) performed. */
279 Stats::Scalar<> fastWrites;
279 Stats::Scalar fastWrites;
280
281 /** The number of cache copies performed. */
280
281 /** The number of cache copies performed. */
282 Stats::Scalar<> cacheCopies;
282 Stats::Scalar cacheCopies;
283
284 /** Number of blocks written back per thread. */
283
284 /** Number of blocks written back per thread. */
285 Stats::Vector<> writebacks;
285 Stats::Vector writebacks;
286
287 /** Number of misses that hit in the MSHRs per command and thread. */
286
287 /** Number of misses that hit in the MSHRs per command and thread. */
288 Stats::Vector<> mshr_hits[MemCmd::NUM_MEM_CMDS];
288 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
289 /** Demand misses that hit in the MSHRs. */
290 Stats::Formula demandMshrHits;
291 /** Total number of misses that hit in the MSHRs. */
292 Stats::Formula overallMshrHits;
293
294 /** Number of misses that miss in the MSHRs, per command and thread. */
289 /** Demand misses that hit in the MSHRs. */
290 Stats::Formula demandMshrHits;
291 /** Total number of misses that hit in the MSHRs. */
292 Stats::Formula overallMshrHits;
293
294 /** Number of misses that miss in the MSHRs, per command and thread. */
295 Stats::Vector<> mshr_misses[MemCmd::NUM_MEM_CMDS];
295 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
296 /** Demand misses that miss in the MSHRs. */
297 Stats::Formula demandMshrMisses;
298 /** Total number of misses that miss in the MSHRs. */
299 Stats::Formula overallMshrMisses;
300
301 /** Number of misses that miss in the MSHRs, per command and thread. */
296 /** Demand misses that miss in the MSHRs. */
297 Stats::Formula demandMshrMisses;
298 /** Total number of misses that miss in the MSHRs. */
299 Stats::Formula overallMshrMisses;
300
301 /** Number of misses that miss in the MSHRs, per command and thread. */
302 Stats::Vector<> mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
302 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
303 /** Total number of misses that miss in the MSHRs. */
304 Stats::Formula overallMshrUncacheable;
305
306 /** Total cycle latency of each MSHR miss, per command and thread. */
303 /** Total number of misses that miss in the MSHRs. */
304 Stats::Formula overallMshrUncacheable;
305
306 /** Total cycle latency of each MSHR miss, per command and thread. */
307 Stats::Vector<> mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
307 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
308 /** Total cycle latency of demand MSHR misses. */
309 Stats::Formula demandMshrMissLatency;
310 /** Total cycle latency of overall MSHR misses. */
311 Stats::Formula overallMshrMissLatency;
312
313 /** Total cycle latency of each MSHR miss, per command and thread. */
308 /** Total cycle latency of demand MSHR misses. */
309 Stats::Formula demandMshrMissLatency;
310 /** Total cycle latency of overall MSHR misses. */
311 Stats::Formula overallMshrMissLatency;
312
313 /** Total cycle latency of each MSHR miss, per command and thread. */
314 Stats::Vector<> mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
314 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
315 /** Total cycle latency of overall MSHR misses. */
316 Stats::Formula overallMshrUncacheableLatency;
317
318 /** The total number of MSHR accesses per command and thread. */
319 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
320 /** The total number of demand MSHR accesses. */
321 Stats::Formula demandMshrAccesses;
322 /** The total number of MSHR accesses. */

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337 Stats::Formula overallAvgMshrMissLatency;
338
339 /** The average latency of an MSHR miss, per command and thread. */
340 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
341 /** The average overall latency of an MSHR miss. */
342 Stats::Formula overallAvgMshrUncacheableLatency;
343
344 /** The number of times a thread hit its MSHR cap. */
315 /** Total cycle latency of overall MSHR misses. */
316 Stats::Formula overallMshrUncacheableLatency;
317
318 /** The total number of MSHR accesses per command and thread. */
319 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
320 /** The total number of demand MSHR accesses. */
321 Stats::Formula demandMshrAccesses;
322 /** The total number of MSHR accesses. */

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337 Stats::Formula overallAvgMshrMissLatency;
338
339 /** The average latency of an MSHR miss, per command and thread. */
340 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
341 /** The average overall latency of an MSHR miss. */
342 Stats::Formula overallAvgMshrUncacheableLatency;
343
344 /** The number of times a thread hit its MSHR cap. */
345 Stats::Vector<> mshr_cap_events;
345 Stats::Vector mshr_cap_events;
346 /** The number of times software prefetches caused the MSHR to block. */
346 /** The number of times software prefetches caused the MSHR to block. */
347 Stats::Vector<> soft_prefetch_mshr_full;
347 Stats::Vector soft_prefetch_mshr_full;
348
348
349 Stats::Scalar<> mshr_no_allocate_misses;
349 Stats::Scalar mshr_no_allocate_misses;
350
351 /**
352 * @}
353 */
354
355 /**
356 * Register stats for this object.
357 */

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351 /**
352 * @}
353 */
354
355 /**
356 * Register stats for this object.
357 */

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