base.hh (13947:4cf8087cab09) | base.hh (13948:f8666d4d5855) |
---|---|
1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 440 unchanged lines hidden (view full) --- 449 Cycles calculateAccessLatency(const CacheBlk* blk, const uint32_t delay, 450 const Cycles lookup_lat) const; 451 452 /** 453 * Does all the processing necessary to perform the provided request. 454 * @param pkt The memory request to perform. 455 * @param blk The cache block to be updated. 456 * @param lat The latency of the access. | 1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 440 unchanged lines hidden (view full) --- 449 Cycles calculateAccessLatency(const CacheBlk* blk, const uint32_t delay, 450 const Cycles lookup_lat) const; 451 452 /** 453 * Does all the processing necessary to perform the provided request. 454 * @param pkt The memory request to perform. 455 * @param blk The cache block to be updated. 456 * @param lat The latency of the access. |
457 * @param writebacks List for any writebacks that need to be performed. | |
458 * @return Boolean indicating whether the request was satisfied. 459 */ | 457 * @return Boolean indicating whether the request was satisfied. 458 */ |
460 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 461 PacketList &writebacks); | 459 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat); |
462 463 /* 464 * Handle a timing request that hit in the cache 465 * 466 * @param ptk The request packet 467 * @param blk The referenced block 468 * @param request_time The tick at which the block lookup is compete 469 */ --- 76 unchanged lines hidden (view full) --- 546 * Handle a request in atomic mode that missed in this cache 547 * 548 * Creates a downstream request, sends it to the memory below and 549 * handles the response. As we are in atomic mode all operations 550 * are performed immediately. 551 * 552 * @param pkt The packet with the requests 553 * @param blk The referenced block | 460 461 /* 462 * Handle a timing request that hit in the cache 463 * 464 * @param ptk The request packet 465 * @param blk The referenced block 466 * @param request_time The tick at which the block lookup is compete 467 */ --- 76 unchanged lines hidden (view full) --- 544 * Handle a request in atomic mode that missed in this cache 545 * 546 * Creates a downstream request, sends it to the memory below and 547 * handles the response. As we are in atomic mode all operations 548 * are performed immediately. 549 * 550 * @param pkt The packet with the requests 551 * @param blk The referenced block |
554 * @param writebacks A list with packets for any performed writebacks | |
555 * @return Cycles for handling the request 556 */ | 552 * @return Cycles for handling the request 553 */ |
557 virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk, 558 PacketList &writebacks) = 0; | 554 virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *&blk) = 0; |
559 560 /** 561 * Performs the access specified by the request. 562 * @param pkt The request to perform. 563 * @return The number of ticks required for the access. 564 */ 565 virtual Tick recvAtomic(PacketPtr pkt); 566 --- 23 unchanged lines hidden (view full) --- 590 * from the MSHR queue, a buffered write from the write buffer, or 591 * something from the prefetcher. This function is responsible 592 * for prioritizing among those sources on the fly. 593 */ 594 QueueEntry* getNextQueueEntry(); 595 596 /** 597 * Insert writebacks into the write buffer | 555 556 /** 557 * Performs the access specified by the request. 558 * @param pkt The request to perform. 559 * @return The number of ticks required for the access. 560 */ 561 virtual Tick recvAtomic(PacketPtr pkt); 562 --- 23 unchanged lines hidden (view full) --- 586 * from the MSHR queue, a buffered write from the write buffer, or 587 * something from the prefetcher. This function is responsible 588 * for prioritizing among those sources on the fly. 589 */ 590 QueueEntry* getNextQueueEntry(); 591 592 /** 593 * Insert writebacks into the write buffer |
594 * 595 * @param pkt The writeback packet. 596 * @param forward_time Tick to which the writeback should be scheduled. |
|
598 */ | 597 */ |
599 virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0; | 598 virtual void doWritebacks(PacketPtr pkt, Tick forward_time) = 0; |
600 601 /** | 599 600 /** |
602 * Send writebacks down the memory hierarchy in atomic mode | 601 * Send writebacks down the memory hierarchy in atomic mode. 602 * 603 * @param pkt The writeback packet. |
603 */ | 604 */ |
604 virtual void doWritebacksAtomic(PacketList& writebacks) = 0; | 605 virtual void doWritebacksAtomic(PacketPtr pkt) = 0; |
605 606 /** 607 * Create an appropriate downstream bus request packet. 608 * 609 * Creates a new packet with the request to be send to the memory 610 * below, or nullptr if the current request in cpu_pkt should just 611 * be forwarded on. 612 * --- 29 unchanged lines hidden (view full) --- 642 643 /** 644 * Send the outstanding tempBlock writeback. To be called after 645 * recvAtomic finishes in cases where the block we filled is in 646 * fact the tempBlock, and now needs to be written back. 647 */ 648 void writebackTempBlockAtomic() { 649 assert(tempBlockWriteback != nullptr); | 606 607 /** 608 * Create an appropriate downstream bus request packet. 609 * 610 * Creates a new packet with the request to be send to the memory 611 * below, or nullptr if the current request in cpu_pkt should just 612 * be forwarded on. 613 * --- 29 unchanged lines hidden (view full) --- 643 644 /** 645 * Send the outstanding tempBlock writeback. To be called after 646 * recvAtomic finishes in cases where the block we filled is in 647 * fact the tempBlock, and now needs to be written back. 648 */ 649 void writebackTempBlockAtomic() { 650 assert(tempBlockWriteback != nullptr); |
650 PacketList writebacks{tempBlockWriteback}; 651 doWritebacksAtomic(writebacks); | 651 doWritebacksAtomic(tempBlockWriteback); |
652 tempBlockWriteback = nullptr; 653 } 654 655 /** 656 * An event to writeback the tempBlock after recvAtomic 657 * finishes. To avoid other calls to recvAtomic getting in 658 * between, we create this event with a higher priority. 659 */ --- 15 unchanged lines hidden (view full) --- 675 * This implementation uses the first approach. 676 * 677 * Notice that this is only called for writebacks, which means that L1 678 * caches (which see regular Writes), do not support compression. 679 * @sa CompressedTags 680 * 681 * @param blk The block to be overwriten. 682 * @param data A pointer to the data to be compressed (blk's new data). | 652 tempBlockWriteback = nullptr; 653 } 654 655 /** 656 * An event to writeback the tempBlock after recvAtomic 657 * finishes. To avoid other calls to recvAtomic getting in 658 * between, we create this event with a higher priority. 659 */ --- 15 unchanged lines hidden (view full) --- 675 * This implementation uses the first approach. 676 * 677 * Notice that this is only called for writebacks, which means that L1 678 * caches (which see regular Writes), do not support compression. 679 * @sa CompressedTags 680 * 681 * @param blk The block to be overwriten. 682 * @param data A pointer to the data to be compressed (blk's new data). |
683 * @param writebacks List for any writebacks that need to be performed. | 683 * @param delay The delay until the packet's metadata is present. 684 * @param tag_latency Latency to access the tags of the replacement victim. |
684 * @return Whether operation is successful or not. 685 */ 686 bool updateCompressionData(CacheBlk *blk, const uint64_t* data, | 685 * @return Whether operation is successful or not. 686 */ 687 bool updateCompressionData(CacheBlk *blk, const uint64_t* data, |
687 PacketList &writebacks); | 688 uint32_t delay, Cycles tag_latency); |
688 689 /** 690 * Perform any necessary updates to the block and perform any data 691 * exchange between the packet and the block. The flags of the 692 * packet are also set accordingly. 693 * 694 * @param pkt Request packet from upstream that hit a block 695 * @param blk Cache block that the packet hit --- 16 unchanged lines hidden (view full) --- 712 void maintainClusivity(bool from_cache, CacheBlk *blk); 713 714 /** 715 * Handle a fill operation caused by a received packet. 716 * 717 * Populates a cache block and handles all outstanding requests for the 718 * satisfied fill request. This version takes two memory requests. One 719 * contains the fill data, the other is an optional target to satisfy. | 689 690 /** 691 * Perform any necessary updates to the block and perform any data 692 * exchange between the packet and the block. The flags of the 693 * packet are also set accordingly. 694 * 695 * @param pkt Request packet from upstream that hit a block 696 * @param blk Cache block that the packet hit --- 16 unchanged lines hidden (view full) --- 713 void maintainClusivity(bool from_cache, CacheBlk *blk); 714 715 /** 716 * Handle a fill operation caused by a received packet. 717 * 718 * Populates a cache block and handles all outstanding requests for the 719 * satisfied fill request. This version takes two memory requests. One 720 * contains the fill data, the other is an optional target to satisfy. |
720 * Note that the reason we return a list of writebacks rather than 721 * inserting them directly in the write buffer is that this function 722 * is called by both atomic and timing-mode accesses, and in atomic 723 * mode we don't mess with the write buffer (we just perform the 724 * writebacks atomically once the original request is complete). | |
725 * 726 * @param pkt The memory request with the fill data. 727 * @param blk The cache block if it already exists. | 721 * 722 * @param pkt The memory request with the fill data. 723 * @param blk The cache block if it already exists. |
728 * @param writebacks List for any writebacks that need to be performed. | |
729 * @param allocate Whether to allocate a block or use the temp block 730 * @return Pointer to the new cache block. 731 */ | 724 * @param allocate Whether to allocate a block or use the temp block 725 * @return Pointer to the new cache block. 726 */ |
732 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, 733 PacketList &writebacks, bool allocate); | 727 CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk, bool allocate); |
734 735 /** | 728 729 /** |
736 * Allocate a new block and perform any necessary writebacks | 730 * Allocate a new block for the packet's data. The victim block might be 731 * valid, and thus the necessary writebacks are done. May return nullptr 732 * if there are no replaceable blocks. If a replaceable block is found, 733 * it inserts the new block in its place. The new block, however, is not 734 * set as valid yet. |
737 * | 735 * |
738 * Find a victim block and if necessary prepare writebacks for any 739 * existing data. May return nullptr if there are no replaceable 740 * blocks. If a replaceable block is found, it inserts the new block in 741 * its place. The new block, however, is not set as valid yet. 742 * | |
743 * @param pkt Packet holding the address to update | 736 * @param pkt Packet holding the address to update |
744 * @param writebacks A list of writeback packets for the evicted blocks | 737 * @param tag_latency Latency to access the tags of the replacement victim. |
745 * @return the allocated block 746 */ | 738 * @return the allocated block 739 */ |
747 CacheBlk *allocateBlock(const PacketPtr pkt, PacketList &writebacks); | 740 CacheBlk *allocateBlock(const PacketPtr pkt, Cycles tag_latency); 741 |
748 /** 749 * Evict a cache block. 750 * 751 * Performs a writeback if necesssary and invalidates the block 752 * 753 * @param blk Block to invalidate 754 * @return A packet with the writeback, can be nullptr 755 */ 756 M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0; 757 758 /** 759 * Evict a cache block. 760 * 761 * Performs a writeback if necesssary and invalidates the block 762 * 763 * @param blk Block to invalidate | 742 /** 743 * Evict a cache block. 744 * 745 * Performs a writeback if necesssary and invalidates the block 746 * 747 * @param blk Block to invalidate 748 * @return A packet with the writeback, can be nullptr 749 */ 750 M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0; 751 752 /** 753 * Evict a cache block. 754 * 755 * Performs a writeback if necesssary and invalidates the block 756 * 757 * @param blk Block to invalidate |
764 * @param writebacks Return a list of packets with writebacks | 758 * @param forward_time Tick to which the writeback should be scheduled if 759 * in timing mode. |
765 */ | 760 */ |
766 void evictBlock(CacheBlk *blk, PacketList &writebacks); | 761 void evictBlock(CacheBlk *blk, Tick forward_time); |
767 768 /** 769 * Invalidate a cache block. 770 * 771 * @param blk Block to invalidate 772 */ 773 void invalidateBlock(CacheBlk *blk); 774 --- 631 unchanged lines hidden --- | 762 763 /** 764 * Invalidate a cache block. 765 * 766 * @param blk Block to invalidate 767 */ 768 void invalidateBlock(CacheBlk *blk); 769 --- 631 unchanged lines hidden --- |