base.hh (13892:0182a0601f66) | base.hh (13945:a573bed35a8b) |
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1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 50 unchanged lines hidden (view full) --- 59#include "base/addr_range.hh" 60#include "base/statistics.hh" 61#include "base/trace.hh" 62#include "base/types.hh" 63#include "debug/Cache.hh" 64#include "debug/CachePort.hh" 65#include "enums/Clusivity.hh" 66#include "mem/cache/cache_blk.hh" | 1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 50 unchanged lines hidden (view full) --- 59#include "base/addr_range.hh" 60#include "base/statistics.hh" 61#include "base/trace.hh" 62#include "base/types.hh" 63#include "debug/Cache.hh" 64#include "debug/CachePort.hh" 65#include "enums/Clusivity.hh" 66#include "mem/cache/cache_blk.hh" |
67#include "mem/cache/compressors/base.hh" |
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67#include "mem/cache/mshr_queue.hh" 68#include "mem/cache/tags/base.hh" 69#include "mem/cache/write_queue.hh" 70#include "mem/cache/write_queue_entry.hh" 71#include "mem/packet.hh" 72#include "mem/packet_queue.hh" 73#include "mem/qport.hh" 74#include "mem/request.hh" --- 244 unchanged lines hidden (view full) --- 319 MSHRQueue mshrQueue; 320 321 /** Write/writeback buffer */ 322 WriteQueue writeBuffer; 323 324 /** Tag and data Storage */ 325 BaseTags *tags; 326 | 68#include "mem/cache/mshr_queue.hh" 69#include "mem/cache/tags/base.hh" 70#include "mem/cache/write_queue.hh" 71#include "mem/cache/write_queue_entry.hh" 72#include "mem/packet.hh" 73#include "mem/packet_queue.hh" 74#include "mem/qport.hh" 75#include "mem/request.hh" --- 244 unchanged lines hidden (view full) --- 320 MSHRQueue mshrQueue; 321 322 /** Write/writeback buffer */ 323 WriteQueue writeBuffer; 324 325 /** Tag and data Storage */ 326 BaseTags *tags; 327 |
328 /** Compression method being used. */ 329 BaseCacheCompressor* compressor; 330 |
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327 /** Prefetcher */ 328 BasePrefetcher *prefetcher; 329 330 /** To probe when a cache hit occurs */ 331 ProbePointArg<PacketPtr> *ppHit; 332 333 /** To probe when a cache miss occurs */ 334 ProbePointArg<PacketPtr> *ppMiss; --- 730 unchanged lines hidden (view full) --- 1065 1066 void allocateWriteBuffer(PacketPtr pkt, Tick time) 1067 { 1068 // should only see writes or clean evicts here 1069 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict); 1070 1071 Addr blk_addr = pkt->getBlockAddr(blkSize); 1072 | 331 /** Prefetcher */ 332 BasePrefetcher *prefetcher; 333 334 /** To probe when a cache hit occurs */ 335 ProbePointArg<PacketPtr> *ppHit; 336 337 /** To probe when a cache miss occurs */ 338 ProbePointArg<PacketPtr> *ppMiss; --- 730 unchanged lines hidden (view full) --- 1069 1070 void allocateWriteBuffer(PacketPtr pkt, Tick time) 1071 { 1072 // should only see writes or clean evicts here 1073 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict); 1074 1075 Addr blk_addr = pkt->getBlockAddr(blkSize); 1076 |
1077 // If using compression, on evictions the block is decompressed and 1078 // the operation's latency is added to the payload delay. Consume 1079 // that payload delay here, meaning that the data is always stored 1080 // uncompressed in the writebuffer 1081 if (compressor) { 1082 time += pkt->payloadDelay; 1083 pkt->payloadDelay = 0; 1084 } 1085 |
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1073 WriteQueueEntry *wq_entry = 1074 writeBuffer.findMatch(blk_addr, pkt->isSecure()); 1075 if (wq_entry && !wq_entry->inService) { 1076 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print()); 1077 } 1078 1079 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++); 1080 --- 282 unchanged lines hidden --- | 1086 WriteQueueEntry *wq_entry = 1087 writeBuffer.findMatch(blk_addr, pkt->isSecure()); 1088 if (wq_entry && !wq_entry->inService) { 1089 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print()); 1090 } 1091 1092 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++); 1093 --- 282 unchanged lines hidden --- |