base.hh (13860:8f8df5b68439) | base.hh (13892:0182a0601f66) |
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1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 54 unchanged lines hidden (view full) --- 63#include "debug/Cache.hh" 64#include "debug/CachePort.hh" 65#include "enums/Clusivity.hh" 66#include "mem/cache/cache_blk.hh" 67#include "mem/cache/mshr_queue.hh" 68#include "mem/cache/tags/base.hh" 69#include "mem/cache/write_queue.hh" 70#include "mem/cache/write_queue_entry.hh" | 1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 54 unchanged lines hidden (view full) --- 63#include "debug/Cache.hh" 64#include "debug/CachePort.hh" 65#include "enums/Clusivity.hh" 66#include "mem/cache/cache_blk.hh" 67#include "mem/cache/mshr_queue.hh" 68#include "mem/cache/tags/base.hh" 69#include "mem/cache/write_queue.hh" 70#include "mem/cache/write_queue_entry.hh" |
71#include "mem/mem_object.hh" | |
72#include "mem/packet.hh" 73#include "mem/packet_queue.hh" 74#include "mem/qport.hh" 75#include "mem/request.hh" 76#include "params/WriteAllocator.hh" | 71#include "mem/packet.hh" 72#include "mem/packet_queue.hh" 73#include "mem/qport.hh" 74#include "mem/request.hh" 75#include "params/WriteAllocator.hh" |
76#include "sim/clocked_object.hh" |
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77#include "sim/eventq.hh" 78#include "sim/probe/probe.hh" 79#include "sim/serialize.hh" 80#include "sim/sim_exit.hh" 81#include "sim/system.hh" 82 83class BaseMasterPort; 84class BasePrefetcher; 85class BaseSlavePort; 86class MSHR; 87class MasterPort; 88class QueueEntry; 89struct BaseCacheParams; 90 91/** 92 * A basic cache interface. Implements some common functions for speed. 93 */ | 77#include "sim/eventq.hh" 78#include "sim/probe/probe.hh" 79#include "sim/serialize.hh" 80#include "sim/sim_exit.hh" 81#include "sim/system.hh" 82 83class BaseMasterPort; 84class BasePrefetcher; 85class BaseSlavePort; 86class MSHR; 87class MasterPort; 88class QueueEntry; 89struct BaseCacheParams; 90 91/** 92 * A basic cache interface. Implements some common functions for speed. 93 */ |
94class BaseCache : public MemObject | 94class BaseCache : public ClockedObject |
95{ 96 protected: 97 /** 98 * Indexes to enumerate the MSHR queues. 99 */ 100 enum MSHRQueueIndex { 101 MSHRQueue_MSHRs, 102 MSHRQueue_WriteBuffer --- 1260 unchanged lines hidden --- | 95{ 96 protected: 97 /** 98 * Indexes to enumerate the MSHR queues. 99 */ 100 enum MSHRQueueIndex { 101 MSHRQueue_MSHRs, 102 MSHRQueue_WriteBuffer --- 1260 unchanged lines hidden --- |