base.hh (13416:d90887d0c889) base.hh (13418:08101e89101e)
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 405 unchanged lines hidden (view full) ---

414 * block or not.
415 *
416 * @param blk The block to regenerate address.
417 * @return The block's address.
418 */
419 Addr regenerateBlkAddr(CacheBlk* blk);
420
421 /**
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 405 unchanged lines hidden (view full) ---

414 * block or not.
415 *
416 * @param blk The block to regenerate address.
417 * @return The block's address.
418 */
419 Addr regenerateBlkAddr(CacheBlk* blk);
420
421 /**
422 * Calculate access latency in ticks given a tag lookup latency, and
423 * whether access was a hit or miss.
424 *
425 * @param blk The cache block that was accessed.
426 * @param lookup_lat Latency of the respective tag lookup.
427 * @return The number of ticks that pass due to a block access.
428 */
429 Cycles calculateAccessLatency(const CacheBlk* blk,
430 const Cycles lookup_lat) const;
431
432 /**
422 * Does all the processing necessary to perform the provided request.
423 * @param pkt The memory request to perform.
424 * @param blk The cache block to be updated.
425 * @param lat The latency of the access.
426 * @param writebacks List for any writebacks that need to be performed.
427 * @return Boolean indicating whether the request was satisfied.
428 */
429 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,

--- 370 unchanged lines hidden (view full) ---

800
801 /**
802 * The latency of sending reponse to its upper level cache/core on
803 * a linefill. The responseLatency parameter captures this
804 * latency.
805 */
806 const Cycles responseLatency;
807
433 * Does all the processing necessary to perform the provided request.
434 * @param pkt The memory request to perform.
435 * @param blk The cache block to be updated.
436 * @param lat The latency of the access.
437 * @param writebacks List for any writebacks that need to be performed.
438 * @return Boolean indicating whether the request was satisfied.
439 */
440 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,

--- 370 unchanged lines hidden (view full) ---

811
812 /**
813 * The latency of sending reponse to its upper level cache/core on
814 * a linefill. The responseLatency parameter captures this
815 * latency.
816 */
817 const Cycles responseLatency;
818
819 /**
820 * Whether tags and data are accessed sequentially.
821 */
822 const bool sequentialAccess;
823
808 /** The number of targets for each MSHR. */
809 const int numTarget;
810
811 /** Do we forward snoops from mem side port through to cpu side port? */
812 bool forwardSnoops;
813
814 /**
815 * Clusivity with respect to the upstream cache, determining if we

--- 510 unchanged lines hidden --- 		824 /** The number of targets for each MSHR. */
825 const int numTarget;
826
827 /** Do we forward snoops from mem side port through to cpu side port? */
828 bool forwardSnoops;
829
830 /**
831 * Clusivity with respect to the upstream cache, determining if we

--- 510 unchanged lines hidden ---