base.hh (13358:5e1605b47a21) base.hh (13416:d90887d0c889)
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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70#include "mem/cache/write_queue_entry.hh"
71#include "mem/mem_object.hh"
72#include "mem/packet.hh"
73#include "mem/packet_queue.hh"
74#include "mem/qport.hh"
75#include "mem/request.hh"
76#include "params/WriteAllocator.hh"
77#include "sim/eventq.hh"
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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70#include "mem/cache/write_queue_entry.hh"
71#include "mem/mem_object.hh"
72#include "mem/packet.hh"
73#include "mem/packet_queue.hh"
74#include "mem/qport.hh"
75#include "mem/request.hh"
76#include "params/WriteAllocator.hh"
77#include "sim/eventq.hh"
78#include "sim/probe/probe.hh"
78#include "sim/serialize.hh"
79#include "sim/sim_exit.hh"
80#include "sim/system.hh"
81
82class BaseMasterPort;
83class BasePrefetcher;
84class BaseSlavePort;
85class MSHR;

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319 WriteQueue writeBuffer;
320
321 /** Tag and data Storage */
322 BaseTags *tags;
323
324 /** Prefetcher */
325 BasePrefetcher *prefetcher;
326
79#include "sim/serialize.hh"
80#include "sim/sim_exit.hh"
81#include "sim/system.hh"
82
83class BaseMasterPort;
84class BasePrefetcher;
85class BaseSlavePort;
86class MSHR;

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320 WriteQueue writeBuffer;
321
322 /** Tag and data Storage */
323 BaseTags *tags;
324
325 /** Prefetcher */
326 BasePrefetcher *prefetcher;
327
327 /**
328 * Notify the prefetcher on every access, not just misses.
329 */
330 const bool prefetchOnAccess;
328 /** To probe when a cache hit occurs */
329 ProbePointArg<PacketPtr> *ppHit;
331
330
331 /** To probe when a cache miss occurs */
332 ProbePointArg<PacketPtr> *ppMiss;
333
332 /**
333 * The writeAllocator drive optimizations for streaming writes.
334 * It first determines whether a WriteReq MSHR should be delayed,
335 * thus ensuring that we wait longer in cases when we are write
336 * coalescing and allowing all the bytes of the line to be written
337 * before the MSHR packet is sent downstream. This works in unison
338 * with the tracking in the MSHR to check if the entire line is
339 * written. The write mode also affects the behaviour on filling

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984 * @}
985 */
986
987 /**
988 * Register stats for this object.
989 */
990 void regStats() override;
991
334 /**
335 * The writeAllocator drive optimizations for streaming writes.
336 * It first determines whether a WriteReq MSHR should be delayed,
337 * thus ensuring that we wait longer in cases when we are write
338 * coalescing and allowing all the bytes of the line to be written
339 * before the MSHR packet is sent downstream. This works in unison
340 * with the tracking in the MSHR to check if the entire line is
341 * written. The write mode also affects the behaviour on filling

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986 * @}
987 */
988
989 /**
990 * Register stats for this object.
991 */
992 void regStats() override;
993
994 /** Registers probes. */
995 void regProbePoints() override;
996
992 public:
993 BaseCache(const BaseCacheParams *p, unsigned blk_size);
994 ~BaseCache();
995
996 void init() override;
997
998 BaseMasterPort &getMasterPort(const std::string &if_name,
999 PortID idx = InvalidPortID) override;

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1131 void incHitCount(PacketPtr pkt)
1132 {
1133 assert(pkt->req->masterId() < system->maxMasters());
1134 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
1135
1136 }
1137
1138 /**
997 public:
998 BaseCache(const BaseCacheParams *p, unsigned blk_size);
999 ~BaseCache();
1000
1001 void init() override;
1002
1003 BaseMasterPort &getMasterPort(const std::string &if_name,
1004 PortID idx = InvalidPortID) override;

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1136 void incHitCount(PacketPtr pkt)
1137 {
1138 assert(pkt->req->masterId() < system->maxMasters());
1139 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
1140
1141 }
1142
1143 /**
1144 * Checks if the cache is coalescing writes
1145 *
1146 * @return True if the cache is coalescing writes
1147 */
1148 bool coalesce() const;
1149
1150
1151 /**
1139 * Cache block visitor that writes back dirty cache blocks using
1140 * functional writes.
1141 */
1142 void writebackVisitor(CacheBlk &blk);
1143
1144 /**
1145 * Cache block visitor that invalidates all blocks in the cache.
1146 *

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1170
1171 /**
1172 * Serialize the state of the caches
1173 *
1174 * We currently don't support checkpointing cache state, so this panics.
1175 */
1176 void serialize(CheckpointOut &cp) const override;
1177 void unserialize(CheckpointIn &cp) override;
1152 * Cache block visitor that writes back dirty cache blocks using
1153 * functional writes.
1154 */
1155 void writebackVisitor(CacheBlk &blk);
1156
1157 /**
1158 * Cache block visitor that invalidates all blocks in the cache.
1159 *

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1183
1184 /**
1185 * Serialize the state of the caches
1186 *
1187 * We currently don't support checkpointing cache state, so this panics.
1188 */
1189 void serialize(CheckpointOut &cp) const override;
1190 void unserialize(CheckpointIn &cp) override;
1178
1179};
1180
1181/**
1182 * The write allocator inspects write packets and detects streaming
1183 * patterns. The write allocator supports a single stream where writes
1184 * are expected to access consecutive locations and keeps track of
1185 * size of the area covered by the concecutive writes in byteCount.
1186 *

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1192
1193/**
1194 * The write allocator inspects write packets and detects streaming
1195 * patterns. The write allocator supports a single stream where writes
1196 * are expected to access consecutive locations and keeps track of
1197 * size of the area covered by the concecutive writes in byteCount.
1198 *

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