| base.hh (13223:081299f403fe) | base.hh (13350:247e4108a5e8) |
|---|---|
| 1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 552 unchanged lines hidden (view full) --- 561 * Creates a new packet with the request to be send to the memory 562 * below, or nullptr if the current request in cpu_pkt should just 563 * be forwarded on. 564 * 565 * @param cpu_pkt The miss packet that needs to be satisfied. 566 * @param blk The referenced block, can be nullptr. 567 * @param needs_writable Indicates that the block must be writable 568 * even if the request in cpu_pkt doesn't indicate that. | 1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 552 unchanged lines hidden (view full) --- 561 * Creates a new packet with the request to be send to the memory 562 * below, or nullptr if the current request in cpu_pkt should just 563 * be forwarded on. 564 * 565 * @param cpu_pkt The miss packet that needs to be satisfied. 566 * @param blk The referenced block, can be nullptr. 567 * @param needs_writable Indicates that the block must be writable 568 * even if the request in cpu_pkt doesn't indicate that. |
| 569 * @param is_whole_line_write True if there are writes for the 570 * whole line |
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| 569 * @return A packet send to the memory below 570 */ 571 virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, | 571 * @return A packet send to the memory below 572 */ 573 virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, |
| 572 bool needs_writable) const = 0; | 574 bool needs_writable, 575 bool is_whole_line_write) const = 0; |
| 573 574 /** 575 * Determine if clean lines should be written back or not. In 576 * cases where a downstream cache is mostly inclusive we likely 577 * want it to act as a victim cache also for lines that have not 578 * been modified. Hence, we cannot simply drop the line (or send a 579 * clean evict), but rather need to send the actual data. 580 */ --- 581 unchanged lines hidden --- | 576 577 /** 578 * Determine if clean lines should be written back or not. In 579 * cases where a downstream cache is mostly inclusive we likely 580 * want it to act as a victim cache also for lines that have not 581 * been modified. Hence, we cannot simply drop the line (or send a 582 * clean evict), but rather need to send the actual data. 583 */ --- 581 unchanged lines hidden --- |