base.hh (12728:57bdea4f96aa) base.hh (12730:6c2ea88bf129)
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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329 const bool prefetchOnAccess;
330
331 /**
332 * Temporary cache block for occasional transitory use. We use
333 * the tempBlock to fill when allocation fails (e.g., when there
334 * is an outstanding request that accesses the victim block) or
335 * when we want to avoid allocation (e.g., exclusive caches)
336 */
1/*
2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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329 const bool prefetchOnAccess;
330
331 /**
332 * Temporary cache block for occasional transitory use. We use
333 * the tempBlock to fill when allocation fails (e.g., when there
334 * is an outstanding request that accesses the victim block) or
335 * when we want to avoid allocation (e.g., exclusive caches)
336 */
337 CacheBlk *tempBlock;
337 TempCacheBlk *tempBlock;
338
339 /**
340 * Upstream caches need this packet until true is returned, so
341 * hold it for deletion until a subsequent call
342 */
343 std::unique_ptr<Packet> pendingDelete;
344
345 /**

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385 cmd == MemCmd::WriteLineReq ||
386 cmd == MemCmd::ReadReq ||
387 cmd == MemCmd::WriteReq ||
388 cmd.isPrefetch() ||
389 cmd.isLLSC();
390 }
391
392 /**
338
339 /**
340 * Upstream caches need this packet until true is returned, so
341 * hold it for deletion until a subsequent call
342 */
343 std::unique_ptr<Packet> pendingDelete;
344
345 /**

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385 cmd == MemCmd::WriteLineReq ||
386 cmd == MemCmd::ReadReq ||
387 cmd == MemCmd::WriteReq ||
388 cmd.isPrefetch() ||
389 cmd.isLLSC();
390 }
391
392 /**
393 * Regenerate block address using tags.
394 * Block address regeneration depends on whether we're using a temporary
395 * block or not.
396 *
397 * @param blk The block to regenerate address.
398 * @return The block's address.
399 */
400 Addr regenerateBlkAddr(CacheBlk* blk);
401
402 /**
393 * Does all the processing necessary to perform the provided request.
394 * @param pkt The memory request to perform.
395 * @param blk The cache block to be updated.
396 * @param lat The latency of the access.
397 * @param writebacks List for any writebacks that need to be performed.
398 * @return Boolean indicating whether the request was satisfied.
399 */
400 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,

--- 751 unchanged lines hidden --- 		403 * Does all the processing necessary to perform the provided request.
404 * @param pkt The memory request to perform.
405 * @param blk The cache block to be updated.
406 * @param lat The latency of the access.
407 * @param writebacks List for any writebacks that need to be performed.
408 * @return Boolean indicating whether the request was satisfied.
409 */
410 virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,

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