base.hh (11331:cd5c48db28e6) base.hh (11375:f98df9231cdd)
1/*
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/cache/write_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
66#include "mem/mem_object.hh"
67#include "mem/packet.hh"
68#include "mem/qport.hh"
69#include "mem/request.hh"
70#include "params/BaseCache.hh"
71#include "sim/eventq.hh"
72#include "sim/full_system.hh"
73#include "sim/sim_exit.hh"
74#include "sim/system.hh"
75
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 protected:
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88

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185 CacheMasterPort *memSidePort;
186
187 protected:
188
189 /** Miss status registers */
190 MSHRQueue mshrQueue;
191
192 /** Write/writeback buffer */
82 /**
83 * Indexes to enumerate the MSHR queues.
84 */
85 enum MSHRQueueIndex {
86 MSHRQueue_MSHRs,
87 MSHRQueue_WriteBuffer
88 };
89

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186 CacheMasterPort *memSidePort;
187
188 protected:
189
190 /** Miss status registers */
191 MSHRQueue mshrQueue;
192
193 /** Write/writeback buffer */
193 MSHRQueue writeBuffer;
194 WriteQueue writeBuffer;
194
195 /**
195
196 /**
196 * Allocate a buffer, passing the time indicating when schedule an
197 * event to the queued port to go and ask the MSHR and write queue
198 * if they have packets to send.
199 *
200 * allocateBufferInternal() function is called in:
201 * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer);
202 * - MSHR allocateMissBuffer (miss in MSHR queue);
197 * Mark a request as in service (sent downstream in the memory
198 * system), effectively making this MSHR the ordering point.
203 */
199 */
204 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
205 PacketPtr pkt, Tick time,
206 bool sched_send)
200 void markInService(MSHR *mshr, bool pending_modified_resp)
207 {
201 {
208 // check that the address is block aligned since we rely on
209 // this in a number of places when checking for matches and
210 // overlap
211 assert(addr == blockAlign(addr));
202 bool wasFull = mshrQueue.isFull();
203 mshrQueue.markInService(mshr, pending_modified_resp);
212
204
213 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++,
214 allocOnFill(pkt->cmd));
215
216 if (mq->isFull()) {
217 setBlocked((BlockedCause)mq->index);
205 if (wasFull && !mshrQueue.isFull()) {
206 clearBlocked(Blocked_NoMSHRs);
218 }
207 }
219
220 if (sched_send)
221 // schedule the send
222 schedMemSideSendEvent(time);
223
224 return mshr;
225 }
226
208 }
209
227 void markInServiceInternal(MSHR *mshr, bool pending_modified_resp)
210 void markInService(WriteQueueEntry *entry)
228 {
211 {
229 MSHRQueue *mq = mshr->queue;
230 bool wasFull = mq->isFull();
231 mq->markInService(mshr, pending_modified_resp);
232 if (wasFull && !mq->isFull()) {
233 clearBlocked((BlockedCause)mq->index);
212 bool wasFull = writeBuffer.isFull();
213 writeBuffer.markInService(entry);
214
215 if (wasFull && !writeBuffer.isFull()) {
216 clearBlocked(Blocked_NoWBBuffers);
234 }
235 }
236
237 /**
238 * Determine if we should allocate on a fill or not.
239 *
240 * @param cmd Packet command being added as an MSHR target
241 *

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506
507 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
508
509
510 const AddrRangeList &getAddrRanges() const { return addrRanges; }
511
512 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
513 {
217 }
218 }
219
220 /**
221 * Determine if we should allocate on a fill or not.
222 *
223 * @param cmd Packet command being added as an MSHR target
224 *

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489
490 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
491
492
493 const AddrRangeList &getAddrRanges() const { return addrRanges; }
494
495 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
496 {
514 return allocateBufferInternal(&mshrQueue,
515 blockAlign(pkt->getAddr()), blkSize,
516 pkt, time, sched_send);
497 MSHR *mshr = mshrQueue.allocate(blockAlign(pkt->getAddr()), blkSize,
498 pkt, time, order++,
499 allocOnFill(pkt->cmd));
500
501 if (mshrQueue.isFull()) {
502 setBlocked((BlockedCause)MSHRQueue_MSHRs);
503 }
504
505 if (sched_send) {
506 // schedule the send
507 schedMemSideSendEvent(time);
508 }
509
510 return mshr;
517 }
518
511 }
512
519 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time)
513 void allocateWriteBuffer(PacketPtr pkt, Tick time)
520 {
521 // should only see writes or clean evicts here
522 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
523
514 {
515 // should only see writes or clean evicts here
516 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
517
524 return allocateBufferInternal(&writeBuffer,
525 blockAlign(pkt->getAddr()), blkSize,
526 pkt, time, true);
518 Addr blk_addr = blockAlign(pkt->getAddr());
519
520 WriteQueueEntry *wq_entry =
521 writeBuffer.findMatch(blk_addr, pkt->isSecure());
522 if (wq_entry && !wq_entry->inService) {
523 DPRINTF(Cache, "Potential to merge writeback %s to %#llx",
524 pkt->cmdString(), pkt->getAddr());
525 }
526
527 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
528
529 if (writeBuffer.isFull()) {
530 setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
531 }
532
533 // schedule the send
534 schedMemSideSendEvent(time);
527 }
528
529 /**
530 * Returns true if the cache is blocked for accesses.
531 */
532 bool isBlocked() const
533 {
534 return blocked != 0;

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536
537 /**
538 * Returns true if the cache is blocked for accesses.
539 */
540 bool isBlocked() const
541 {
542 return blocked != 0;

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