base.hh (11284:b3926db25371) base.hh (11331:cd5c48db28e6)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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297 * latency.
298 */
299 const Cycles responseLatency;
300
301 /** The number of targets for each MSHR. */
302 const int numTarget;
303
304 /** Do we forward snoops from mem side port through to cpu side port? */
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 288 unchanged lines hidden (view full) ---

297 * latency.
298 */
299 const Cycles responseLatency;
300
301 /** The number of targets for each MSHR. */
302 const int numTarget;
303
304 /** Do we forward snoops from mem side port through to cpu side port? */
305 const bool forwardSnoops;
305 bool forwardSnoops;
306
307 /**
308 * Is this cache read only, for example the instruction cache, or
309 * table-walker cache. A cache that is read only should never see
310 * any writes, and should never get any dirty data (and hence
311 * never have to do any writebacks).
312 */
313 const bool isReadOnly;

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307 /**
308 * Is this cache read only, for example the instruction cache, or
309 * table-walker cache. A cache that is read only should never see
310 * any writes, and should never get any dirty data (and hence
311 * never have to do any writebacks).
312 */
313 const bool isReadOnly;

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