base.hh (11197:f8fdd931e674) base.hh (11199:929fd978ab4e)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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516 pkt, time, sched_send);
517 }
518
519 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time)
520 {
521 // should only see writes or clean evicts here
522 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
523
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 507 unchanged lines hidden (view full) ---

516 pkt, time, sched_send);
517 }
518
519 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time)
520 {
521 // should only see writes or clean evicts here
522 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
523
524 // if this is a read-only cache we should never see any writes
525 assert(!(isReadOnly && pkt->isWrite()));
526
527 return allocateBufferInternal(&writeBuffer,
528 blockAlign(pkt->getAddr()), blkSize,
529 pkt, time, true);
530 }
531
532 /**
533 * Returns true if the cache is blocked for accesses.
534 */

--- 78 unchanged lines hidden --- 		524 return allocateBufferInternal(&writeBuffer,
525 blockAlign(pkt->getAddr()), blkSize,
526 pkt, time, true);
527 }
528
529 /**
530 * Returns true if the cache is blocked for accesses.
531 */

--- 78 unchanged lines hidden ---