base.hh (11053:62544e45c0f4) base.hh (11191:9eabb2bf349b)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 494 unchanged lines hidden (view full) ---

503 {
504 return allocateBufferInternal(&mshrQueue,
505 blockAlign(pkt->getAddr()), blkSize,
506 pkt, time, sched_send);
507 }
508
509 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time)
510 {
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 494 unchanged lines hidden (view full) ---

503 {
504 return allocateBufferInternal(&mshrQueue,
505 blockAlign(pkt->getAddr()), blkSize,
506 pkt, time, sched_send);
507 }
508
509 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time)
510 {
511 // should only see clean evictions in a read-only cache
512 assert(!isReadOnly || pkt->cmd == MemCmd::CleanEvict);
513 assert(pkt->isWrite() && !pkt->isRead());
511 // should only see writes or clean evicts here
512 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
513
514 // if this is a read-only cache we should never see any writes
515 assert(!(isReadOnly && pkt->isWrite()));
516
514 return allocateBufferInternal(&writeBuffer,
515 blockAlign(pkt->getAddr()), blkSize,
516 pkt, time, true);
517 }
518
519 /**
520 * Returns true if the cache is blocked for accesses.
521 */

--- 78 unchanged lines hidden --- 		517 return allocateBufferInternal(&writeBuffer,
518 blockAlign(pkt->getAddr()), blkSize,
519 pkt, time, true);
520 }
521
522 /**
523 * Returns true if the cache is blocked for accesses.
524 */

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