base.hh (11051:81b1f46061c8) base.hh (11053:62544e45c0f4)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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468 */
469
470 /**
471 * Register stats for this object.
472 */
473 virtual void regStats();
474
475 public:
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 459 unchanged lines hidden (view full) ---

468 */
469
470 /**
471 * Register stats for this object.
472 */
473 virtual void regStats();
474
475 public:
476 typedef BaseCacheParams Params;
477 BaseCache(const Params *p);
476 BaseCache(const BaseCacheParams *p, unsigned blk_size);
478 ~BaseCache() {}
479
480 virtual void init();
481
482 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
483 PortID idx = InvalidPortID);
484 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
485 PortID idx = InvalidPortID);

--- 115 unchanged lines hidden --- 		477 ~BaseCache() {}
478
479 virtual void init();
480
481 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
482 PortID idx = InvalidPortID);
483 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
484 PortID idx = InvalidPortID);

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