base.hh (10912:b99a6662d7c2) base.hh (10942:224c85495f96)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
100 protected:
101
102 /**
103 * A cache master port is used for the memory-side port of the
104 * cache, and in addition to the basic timing port that only sends
105 * response packets through a transmit list, it also offers the
106 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
107 * writebacks). The send event is scheduled through schedSendEvent,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry outstanding.
129 */
108 * and the sendDeferredPacket of the timing port is modified to
109 * consider both the transmit list and the requests from the MSHR.
110 */
111 class CacheMasterPort : public QueuedMasterPort
112 {
113
114 public:
115
116 /**
117 * Schedule a send of a request packet (from the MSHR). Note
118 * that we could already have a retry outstanding.
119 */
130 void requestBus(RequestCause cause, Tick time)
120 void schedSendEvent(Tick time)
131 {
121 {
132 DPRINTF(CachePort, "Scheduling request at %llu due to %d\n",
133 time, cause);
122 DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
134 reqQueue.schedSendEvent(time);
135 }
136
137 protected:
138
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 ReqPacketQueue &_reqQueue,
141 SnoopRespPacketQueue &_snoopRespQueue) :

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208 * event to the queued port to go and ask the MSHR and write queue
209 * if they have packets to send.
210 *
211 * allocateBufferInternal() function is called in:
212 * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer);
213 * - MSHR allocateMissBuffer (miss in MSHR queue);
214 */
215 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
123 reqQueue.schedSendEvent(time);
124 }
125
126 protected:
127
128 CacheMasterPort(const std::string &_name, BaseCache *_cache,
129 ReqPacketQueue &_reqQueue,
130 SnoopRespPacketQueue &_snoopRespQueue) :

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197 * event to the queued port to go and ask the MSHR and write queue
198 * if they have packets to send.
199 *
200 * allocateBufferInternal() function is called in:
201 * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer);
202 * - MSHR allocateMissBuffer (miss in MSHR queue);
203 */
204 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
216 PacketPtr pkt, Tick time, bool requestBus)
205 PacketPtr pkt, Tick time,
206 bool sched_send)
217 {
218 // check that the address is block aligned since we rely on
219 // this in a number of places when checking for matches and
220 // overlap
221 assert(addr == blockAlign(addr));
222
223 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
224
225 if (mq->isFull()) {
226 setBlocked((BlockedCause)mq->index);
227 }
228
207 {
208 // check that the address is block aligned since we rely on
209 // this in a number of places when checking for matches and
210 // overlap
211 assert(addr == blockAlign(addr));
212
213 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
214
215 if (mq->isFull()) {
216 setBlocked((BlockedCause)mq->index);
217 }
218
229 if (requestBus) {
230 requestMemSideBus((RequestCause)mq->index, time);
231 }
219 if (sched_send)
220 // schedule the send
221 schedMemSideSendEvent(time);
232
233 return mshr;
234 }
235
236 void markInServiceInternal(MSHR *mshr, bool pending_dirty_resp)
237 {
238 MSHRQueue *mq = mshr->queue;
239 bool wasFull = mq->isFull();

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505 }
506
507
508 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
509
510
511 const AddrRangeList &getAddrRanges() const { return addrRanges; }
512
222
223 return mshr;
224 }
225
226 void markInServiceInternal(MSHR *mshr, bool pending_dirty_resp)
227 {
228 MSHRQueue *mq = mshr->queue;
229 bool wasFull = mq->isFull();

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495 }
496
497
498 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
499
500
501 const AddrRangeList &getAddrRanges() const { return addrRanges; }
502
513 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
503 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
514 {
515 return allocateBufferInternal(&mshrQueue,
516 blockAlign(pkt->getAddr()), blkSize,
504 {
505 return allocateBufferInternal(&mshrQueue,
506 blockAlign(pkt->getAddr()), blkSize,
517 pkt, time, requestBus);
507 pkt, time, sched_send);
518 }
519
508 }
509
520 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
510 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time)
521 {
522 // should only see clean evictions in a read-only cache
523 assert(!isReadOnly || pkt->cmd == MemCmd::CleanEvict);
524 assert(pkt->isWrite() && !pkt->isRead());
525 return allocateBufferInternal(&writeBuffer,
526 blockAlign(pkt->getAddr()), blkSize,
511 {
512 // should only see clean evictions in a read-only cache
513 assert(!isReadOnly || pkt->cmd == MemCmd::CleanEvict);
514 assert(pkt->isWrite() && !pkt->isRead());
515 return allocateBufferInternal(&writeBuffer,
516 blockAlign(pkt->getAddr()), blkSize,
527 pkt, time, requestBus);
517 pkt, time, true);
528 }
529
530 /**
531 * Returns true if the cache is blocked for accesses.
532 */
533 bool isBlocked() const
534 {
535 return blocked != 0;

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566 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
567 if (blocked == 0) {
568 blocked_cycles[cause] += curCycle() - blockedCycle;
569 cpuSidePort->clearBlocked();
570 }
571 }
572
573 /**
518 }
519
520 /**
521 * Returns true if the cache is blocked for accesses.
522 */
523 bool isBlocked() const
524 {
525 return blocked != 0;

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556 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
557 if (blocked == 0) {
558 blocked_cycles[cause] += curCycle() - blockedCycle;
559 cpuSidePort->clearBlocked();
560 }
561 }
562
563 /**
574 * Request the master bus for the given cause and time.
575 * @param cause The reason for the request.
576 * @param time The time to make the request.
564 * Schedule a send event for the memory-side port. If already
565 * scheduled, this may reschedule the event at an earlier
566 * time. When the specified time is reached, the port is free to
567 * send either a response, a request, or a prefetch request.
568 *
569 * @param time The time when to attempt sending a packet.
577 */
570 */
578 void requestMemSideBus(RequestCause cause, Tick time)
571 void schedMemSideSendEvent(Tick time)
579 {
572 {
580 memSidePort->requestBus(cause, time);
573 memSidePort->schedSendEvent(time);
581 }
582
574 }
575
583 /**
584 * Clear the master bus request for the given cause.
585 * @param cause The request reason to clear.
586 */
587 void deassertMemSideBusRequest(RequestCause cause)
588 {
589 // Obsolete... we no longer signal bus requests explicitly so
590 // we can't deassert them. Leaving this in as a no-op since
591 // the prefetcher calls it to indicate that it no longer wants
592 // to request a prefetch, and someday that might be
593 // interesting again.
594 }
595
596 virtual bool inCache(Addr addr, bool is_secure) const = 0;
597
598 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
599
600 void incMissCount(PacketPtr pkt)
601 {
602 assert(pkt->req->masterId() < system->maxMasters());
603 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;

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577
578 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
579
580 void incMissCount(PacketPtr pkt)
581 {
582 assert(pkt->req->masterId() < system->maxMasters());
583 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;

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