base.hh (10713:eddb533708cb) base.hh (10714:9ba5e70964a4)
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 115 unchanged lines hidden (view full) ---

124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry outstanding.
129 */
130 void requestBus(RequestCause cause, Tick time)
131 {
1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 115 unchanged lines hidden (view full) ---

124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry outstanding.
129 */
130 void requestBus(RequestCause cause, Tick time)
131 {
132 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
132 DPRINTF(CachePort, "Scheduling request at %llu due to %d\n",
133 time, cause);
133 reqQueue.schedSendEvent(time);
134 }
135
136 protected:
137
138 CacheMasterPort(const std::string &_name, BaseCache *_cache,
139 ReqPacketQueue &_reqQueue,
140 SnoopRespPacketQueue &_snoopRespQueue) :

--- 473 unchanged lines hidden --- 		134 reqQueue.schedSendEvent(time);
135 }
136
137 protected:
138
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 ReqPacketQueue &_reqQueue,
141 SnoopRespPacketQueue &_snoopRespQueue) :

--- 473 unchanged lines hidden ---