base.hh (10020:2f33cb012383) base.hh (10028:fb8c44de891a)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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555 // we can't deassert them. Leaving this in as a no-op since
556 // the prefetcher calls it to indicate that it no longer wants
557 // to request a prefetch, and someday that might be
558 // interesting again.
559 }
560
561 virtual unsigned int drain(DrainManager *dm);
562
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 544 unchanged lines hidden (view full) ---

555 // we can't deassert them. Leaving this in as a no-op since
556 // the prefetcher calls it to indicate that it no longer wants
557 // to request a prefetch, and someday that might be
558 // interesting again.
559 }
560
561 virtual unsigned int drain(DrainManager *dm);
562
563 virtual bool inCache(Addr addr) const = 0;
563 virtual bool inCache(Addr addr, bool is_secure) const = 0;
564
564
565 virtual bool inMissQueue(Addr addr) const = 0;
565 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
566
567 void incMissCount(PacketPtr pkt)
568 {
569 assert(pkt->req->masterId() < system->maxMasters());
570 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
571 pkt->req->incAccessDepth();
572 if (missCount) {
573 --missCount;

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567 void incMissCount(PacketPtr pkt)
568 {
569 assert(pkt->req->masterId() < system->maxMasters());
570 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
571 pkt->req->incAccessDepth();
572 if (missCount) {
573 --missCount;

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