1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Steve Reinhardt 42 * Ron Dreslinski 43 */ 44 45/** 46 * @file 47 * Declares a basic cache interface BaseCache. 48 */ 49 50#ifndef __BASE_CACHE_HH__ 51#define __BASE_CACHE_HH__ 52 53#include <algorithm> 54#include <list> 55#include <string> 56#include <vector> 57 58#include "base/misc.hh" 59#include "base/statistics.hh" 60#include "base/trace.hh" 61#include "base/types.hh" 62#include "debug/Cache.hh" 63#include "debug/CachePort.hh" 64#include "mem/cache/mshr_queue.hh" 65#include "mem/mem_object.hh" 66#include "mem/packet.hh" 67#include "mem/request.hh" 68#include "mem/tport.hh" 69#include "params/BaseCache.hh" 70#include "sim/eventq.hh" 71#include "sim/full_system.hh" 72#include "sim/sim_exit.hh" 73#include "sim/system.hh" 74 75class MSHR; 76/** 77 * A basic cache interface. Implements some common functions for speed. 78 */ 79class BaseCache : public MemObject 80{ 81 /** 82 * Indexes to enumerate the MSHR queues. 83 */ 84 enum MSHRQueueIndex { 85 MSHRQueue_MSHRs, 86 MSHRQueue_WriteBuffer 87 }; 88 89 public: 90 /** 91 * Reasons for caches to be blocked. 92 */ 93 enum BlockedCause { 94 Blocked_NoMSHRs = MSHRQueue_MSHRs, 95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 96 Blocked_NoTargets, 97 NUM_BLOCKED_CAUSES 98 }; 99 100 /** 101 * Reasons for cache to request a bus. 102 */ 103 enum RequestCause { 104 Request_MSHR = MSHRQueue_MSHRs, 105 Request_WB = MSHRQueue_WriteBuffer, 106 Request_PF, 107 NUM_REQUEST_CAUSES 108 }; 109 110 protected: 111 112 /** 113 * A cache master port is used for the memory-side port of the 114 * cache, and in addition to the basic timing port that only sends 115 * response packets through a transmit list, it also offers the 116 * ability to schedule and send request packets (requests & 117 * writebacks). The send event is scheduled through requestBus, 118 * and the sendDeferredPacket of the timing port is modified to 119 * consider both the transmit list and the requests from the MSHR. 120 */ 121 class CacheMasterPort : public SimpleTimingPort 122 { 123 124 public: 125 126 /** 127 * Schedule a send of a request packet (from the MSHR). Note 128 * that we could already have a retry or a transmit list of 129 * responses outstanding. 130 */ 131 void requestBus(RequestCause cause, Tick time) 132 { 133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 134 schedSendEvent(time); 135 } 136 137 void respond(PacketPtr pkt, Tick time) { 138 schedSendTiming(pkt, time); 139 } 140 141 protected: 142 143 CacheMasterPort(const std::string &_name, BaseCache *_cache, 144 const std::string &_label); 145 146 /** 147 * Memory-side port always snoops. 148 * 149 * return always true 150 */ 151 virtual bool isSnooping() { return true; } 152 }; 153 154 /** 155 * A cache slave port is used for the CPU-side port of the cache, 156 * and it is basically a simple timing port that uses a transmit 157 * list for responses to the CPU (or connected master). In 158 * addition, it has the functionality to block the port for 159 * incoming requests. If blocked, the port will issue a retry once 160 * unblocked. 161 */ 162 class CacheSlavePort : public SimpleTimingPort 163 { 164 165 public: 166 167 /** Do not accept any new requests. */ 168 void setBlocked(); 169 170 /** Return to normal operation and accept new requests. */ 171 void clearBlocked(); 172 173 void respond(PacketPtr pkt, Tick time) { 174 schedSendTiming(pkt, time); 175 } 176 177 protected: 178 179 CacheSlavePort(const std::string &_name, BaseCache *_cache, 180 const std::string &_label); 181 182 bool blocked; 183 184 bool mustSendRetry; 185 186 private: 187 188 EventWrapper<Port, &Port::sendRetry> sendRetryEvent; 189 190 }; 191 192 CacheSlavePort *cpuSidePort; 193 CacheMasterPort *memSidePort; 194 195 protected: 196 197 /** Miss status registers */ 198 MSHRQueue mshrQueue; 199 200 /** Write/writeback buffer */ 201 MSHRQueue writeBuffer; 202 203 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 204 PacketPtr pkt, Tick time, bool requestBus) 205 { 206 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 207 208 if (mq->isFull()) { 209 setBlocked((BlockedCause)mq->index); 210 } 211 212 if (requestBus) { 213 requestMemSideBus((RequestCause)mq->index, time); 214 } 215 216 return mshr; 217 } 218 219 void markInServiceInternal(MSHR *mshr, PacketPtr pkt) 220 { 221 MSHRQueue *mq = mshr->queue; 222 bool wasFull = mq->isFull(); 223 mq->markInService(mshr, pkt); 224 if (wasFull && !mq->isFull()) { 225 clearBlocked((BlockedCause)mq->index); 226 } 227 } 228 229 /** Block size of this cache */ 230 const unsigned blkSize; 231 232 /** 233 * The latency of a hit in this device. 234 */ 235 int hitLatency; 236 237 /** The number of targets for each MSHR. */ 238 const int numTarget; 239 240 /** Do we forward snoops from mem side port through to cpu side port? */ 241 bool forwardSnoops; 242 243 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should 244 * never try to forward ownership and similar optimizations to the cpu 245 * side */ 246 bool isTopLevel; 247 248 /** 249 * Bit vector of the blocking reasons for the access path. 250 * @sa #BlockedCause 251 */ 252 uint8_t blocked; 253 254 /** Increasing order number assigned to each incoming request. */ 255 uint64_t order; 256 257 /** Stores time the cache blocked for statistics. */ 258 Tick blockedCycle; 259 260 /** Pointer to the MSHR that has no targets. */ 261 MSHR *noTargetMSHR; 262 263 /** The number of misses to trigger an exit event. */ 264 Counter missCount; 265 266 /** The drain event. */ 267 Event *drainEvent; 268 269 /** 270 * The address range to which the cache responds on the CPU side. 271 * Normally this is all possible memory addresses. */
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443 444 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 445 { 446 assert(!pkt->req->isUncacheable()); 447 return allocateBufferInternal(&mshrQueue, 448 blockAlign(pkt->getAddr()), blkSize, 449 pkt, time, requestBus); 450 } 451 452 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 453 { 454 assert(pkt->isWrite() && !pkt->isRead()); 455 return allocateBufferInternal(&writeBuffer, 456 pkt->getAddr(), pkt->getSize(), 457 pkt, time, requestBus); 458 } 459 460 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus) 461 { 462 assert(pkt->req->isUncacheable()); 463 assert(pkt->isRead()); 464 return allocateBufferInternal(&mshrQueue, 465 pkt->getAddr(), pkt->getSize(), 466 pkt, time, requestBus); 467 } 468 469 /** 470 * Returns true if the cache is blocked for accesses. 471 */ 472 bool isBlocked() 473 { 474 return blocked != 0; 475 } 476 477 /** 478 * Marks the access path of the cache as blocked for the given cause. This 479 * also sets the blocked flag in the slave interface. 480 * @param cause The reason for the cache blocking. 481 */ 482 void setBlocked(BlockedCause cause) 483 { 484 uint8_t flag = 1 << cause; 485 if (blocked == 0) { 486 blocked_causes[cause]++; 487 blockedCycle = curTick(); 488 cpuSidePort->setBlocked(); 489 } 490 blocked |= flag; 491 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 492 } 493 494 /** 495 * Marks the cache as unblocked for the given cause. This also clears the 496 * blocked flags in the appropriate interfaces. 497 * @param cause The newly unblocked cause. 498 * @warning Calling this function can cause a blocked request on the bus to 499 * access the cache. The cache must be in a state to handle that request. 500 */ 501 void clearBlocked(BlockedCause cause) 502 { 503 uint8_t flag = 1 << cause; 504 blocked &= ~flag; 505 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 506 if (blocked == 0) { 507 blocked_cycles[cause] += curTick() - blockedCycle; 508 cpuSidePort->clearBlocked(); 509 } 510 } 511 512 /** 513 * Request the master bus for the given cause and time. 514 * @param cause The reason for the request. 515 * @param time The time to make the request. 516 */ 517 void requestMemSideBus(RequestCause cause, Tick time) 518 { 519 memSidePort->requestBus(cause, time); 520 } 521 522 /** 523 * Clear the master bus request for the given cause. 524 * @param cause The request reason to clear. 525 */ 526 void deassertMemSideBusRequest(RequestCause cause) 527 { 528 // Obsolete... we no longer signal bus requests explicitly so 529 // we can't deassert them. Leaving this in as a no-op since 530 // the prefetcher calls it to indicate that it no longer wants 531 // to request a prefetch, and someday that might be 532 // interesting again. 533 } 534 535 virtual unsigned int drain(Event *de); 536 537 virtual bool inCache(Addr addr) = 0; 538 539 virtual bool inMissQueue(Addr addr) = 0; 540 541 void incMissCount(PacketPtr pkt) 542 { 543 assert(pkt->req->masterId() < system->maxMasters()); 544 misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 545 546 if (missCount) { 547 --missCount; 548 if (missCount == 0) 549 exitSimLoop("A cache reached the maximum miss count"); 550 } 551 } 552 void incHitCount(PacketPtr pkt) 553 { 554 assert(pkt->req->masterId() < system->maxMasters()); 555 hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 556 557 } 558 559}; 560 561#endif //__BASE_CACHE_HH__
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