1/*
2 * Copyright (c) 2012-2013, 2015 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry outstanding.
129 */
130 void requestBus(RequestCause cause, Tick time)
131 {
132 DPRINTF(CachePort, "Scheduling request at %llu due to %d\n",
133 time, cause);
134 reqQueue.schedSendEvent(time);
135 }
136
137 protected:
138
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 ReqPacketQueue &_reqQueue,
141 SnoopRespPacketQueue &_snoopRespQueue) :
142 QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
143 { }
144
145 /**
146 * Memory-side port always snoops.
147 *
148 * @return always true
149 */
150 virtual bool isSnooping() const { return true; }
151 };
152
153 /**
154 * A cache slave port is used for the CPU-side port of the cache,
155 * and it is basically a simple timing port that uses a transmit
156 * list for responses to the CPU (or connected master). In
157 * addition, it has the functionality to block the port for
158 * incoming requests. If blocked, the port will issue a retry once
159 * unblocked.
160 */
161 class CacheSlavePort : public QueuedSlavePort
162 {
163
164 public:
165
166 /** Do not accept any new requests. */
167 void setBlocked();
168
169 /** Return to normal operation and accept new requests. */
170 void clearBlocked();
171
172 bool isBlocked() const { return blocked; }
173
174 protected:
175
176 CacheSlavePort(const std::string &_name, BaseCache *_cache,
177 const std::string &_label);
178
179 /** A normal packet queue used to store responses. */
180 RespPacketQueue queue;
181
182 bool blocked;
183
184 bool mustSendRetry;
185
186 private:
187
188 void processSendRetry();
189
190 EventWrapper<CacheSlavePort,
191 &CacheSlavePort::processSendRetry> sendRetryEvent;
192
193 };
194
195 CacheSlavePort *cpuSidePort;
196 CacheMasterPort *memSidePort;
197
198 protected:
199
200 /** Miss status registers */
201 MSHRQueue mshrQueue;
202
203 /** Write/writeback buffer */
204 MSHRQueue writeBuffer;
205
206 /**
207 * Allocate a buffer, passing the time indicating when schedule an
208 * event to the queued port to go and ask the MSHR and write queue
209 * if they have packets to send.
210 *
211 * allocateBufferInternal() function is called in:
212 * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer);
213 * - MSHR allocateMissBuffer (miss in MSHR queue);
214 */
215 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
216 PacketPtr pkt, Tick time, bool requestBus)
217 {
218 // check that the address is block aligned since we rely on
219 // this in a number of places when checking for matches and
220 // overlap
221 assert(addr == blockAlign(addr));
222
223 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
224
225 if (mq->isFull()) {
226 setBlocked((BlockedCause)mq->index);
227 }
228
229 if (requestBus) {
230 requestMemSideBus((RequestCause)mq->index, time);
231 }
232
233 return mshr;
234 }
235
236 void markInServiceInternal(MSHR *mshr, bool pending_dirty_resp)
237 {
238 MSHRQueue *mq = mshr->queue;
239 bool wasFull = mq->isFull();
240 mq->markInService(mshr, pending_dirty_resp);
241 if (wasFull && !mq->isFull()) {
242 clearBlocked((BlockedCause)mq->index);
243 }
244 }
245
246 /**
247 * Write back dirty blocks in the cache using functional accesses.
248 */
249 virtual void memWriteback() = 0;
250 /**
251 * Invalidates all blocks in the cache.
252 *
253 * @warn Dirty cache lines will not be written back to
254 * memory. Make sure to call functionalWriteback() first if you
255 * want the to write them to memory.
256 */
257 virtual void memInvalidate() = 0;
258 /**
259 * Determine if there are any dirty blocks in the cache.
260 *
261 * \return true if at least one block is dirty, false otherwise.
262 */
263 virtual bool isDirty() const = 0;
264
|
275 /** Block size of this cache */
276 const unsigned blkSize;
277
278 /**
279 * The latency of tag lookup of a cache. It occurs when there is
280 * an access to the cache.
281 */
282 const Cycles lookupLatency;
283
284 /**
285 * This is the forward latency of the cache. It occurs when there
286 * is a cache miss and a request is forwarded downstream, in
287 * particular an outbound miss.
288 */
289 const Cycles forwardLatency;
290
291 /** The latency to fill a cache block */
292 const Cycles fillLatency;
293
294 /**
295 * The latency of sending reponse to its upper level cache/core on
296 * a linefill. The responseLatency parameter captures this
297 * latency.
298 */
299 const Cycles responseLatency;
300
301 /** The number of targets for each MSHR. */
302 const int numTarget;
303
304 /** Do we forward snoops from mem side port through to cpu side port? */
305 const bool forwardSnoops;
306
307 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
308 * never try to forward ownership and similar optimizations to the cpu
309 * side */
310 const bool isTopLevel;
311
312 /**
313 * Bit vector of the blocking reasons for the access path.
314 * @sa #BlockedCause
315 */
316 uint8_t blocked;
317
318 /** Increasing order number assigned to each incoming request. */
319 uint64_t order;
320
321 /** Stores time the cache blocked for statistics. */
322 Cycles blockedCycle;
323
324 /** Pointer to the MSHR that has no targets. */
325 MSHR *noTargetMSHR;
326
327 /** The number of misses to trigger an exit event. */
328 Counter missCount;
329
330 /**
331 * The address range to which the cache responds on the CPU side.
332 * Normally this is all possible memory addresses. */
333 const AddrRangeList addrRanges;
334
335 public:
336 /** System we are currently operating in. */
337 System *system;
338
339 // Statistics
340 /**
341 * @addtogroup CacheStatistics
342 * @{
343 */
344
345 /** Number of hits per thread for each type of command. @sa Packet::Command */
346 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
347 /** Number of hits for demand accesses. */
348 Stats::Formula demandHits;
349 /** Number of hit for all accesses. */
350 Stats::Formula overallHits;
351
352 /** Number of misses per thread for each type of command. @sa Packet::Command */
353 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
354 /** Number of misses for demand accesses. */
355 Stats::Formula demandMisses;
356 /** Number of misses for all accesses. */
357 Stats::Formula overallMisses;
358
359 /**
360 * Total number of cycles per thread/command spent waiting for a miss.
361 * Used to calculate the average miss latency.
362 */
363 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
364 /** Total number of cycles spent waiting for demand misses. */
365 Stats::Formula demandMissLatency;
366 /** Total number of cycles spent waiting for all misses. */
367 Stats::Formula overallMissLatency;
368
369 /** The number of accesses per command and thread. */
370 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
371 /** The number of demand accesses. */
372 Stats::Formula demandAccesses;
373 /** The number of overall accesses. */
374 Stats::Formula overallAccesses;
375
376 /** The miss rate per command and thread. */
377 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
378 /** The miss rate of all demand accesses. */
379 Stats::Formula demandMissRate;
380 /** The miss rate for all accesses. */
381 Stats::Formula overallMissRate;
382
383 /** The average miss latency per command and thread. */
384 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
385 /** The average miss latency for demand misses. */
386 Stats::Formula demandAvgMissLatency;
387 /** The average miss latency for all misses. */
388 Stats::Formula overallAvgMissLatency;
389
390 /** The total number of cycles blocked for each blocked cause. */
391 Stats::Vector blocked_cycles;
392 /** The number of times this cache blocked for each blocked cause. */
393 Stats::Vector blocked_causes;
394
395 /** The average number of cycles blocked for each blocked cause. */
396 Stats::Formula avg_blocked;
397
398 /** The number of fast writes (WH64) performed. */
399 Stats::Scalar fastWrites;
400
401 /** The number of cache copies performed. */
402 Stats::Scalar cacheCopies;
403
404 /** Number of blocks written back per thread. */
405 Stats::Vector writebacks;
406
407 /** Number of misses that hit in the MSHRs per command and thread. */
408 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
409 /** Demand misses that hit in the MSHRs. */
410 Stats::Formula demandMshrHits;
411 /** Total number of misses that hit in the MSHRs. */
412 Stats::Formula overallMshrHits;
413
414 /** Number of misses that miss in the MSHRs, per command and thread. */
415 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
416 /** Demand misses that miss in the MSHRs. */
417 Stats::Formula demandMshrMisses;
418 /** Total number of misses that miss in the MSHRs. */
419 Stats::Formula overallMshrMisses;
420
421 /** Number of misses that miss in the MSHRs, per command and thread. */
422 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
423 /** Total number of misses that miss in the MSHRs. */
424 Stats::Formula overallMshrUncacheable;
425
426 /** Total cycle latency of each MSHR miss, per command and thread. */
427 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
428 /** Total cycle latency of demand MSHR misses. */
429 Stats::Formula demandMshrMissLatency;
430 /** Total cycle latency of overall MSHR misses. */
431 Stats::Formula overallMshrMissLatency;
432
433 /** Total cycle latency of each MSHR miss, per command and thread. */
434 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
435 /** Total cycle latency of overall MSHR misses. */
436 Stats::Formula overallMshrUncacheableLatency;
437
438#if 0
439 /** The total number of MSHR accesses per command and thread. */
440 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
441 /** The total number of demand MSHR accesses. */
442 Stats::Formula demandMshrAccesses;
443 /** The total number of MSHR accesses. */
444 Stats::Formula overallMshrAccesses;
445#endif
446
447 /** The miss rate in the MSHRs pre command and thread. */
448 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
449 /** The demand miss rate in the MSHRs. */
450 Stats::Formula demandMshrMissRate;
451 /** The overall miss rate in the MSHRs. */
452 Stats::Formula overallMshrMissRate;
453
454 /** The average latency of an MSHR miss, per command and thread. */
455 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
456 /** The average latency of a demand MSHR miss. */
457 Stats::Formula demandAvgMshrMissLatency;
458 /** The average overall latency of an MSHR miss. */
459 Stats::Formula overallAvgMshrMissLatency;
460
461 /** The average latency of an MSHR miss, per command and thread. */
462 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
463 /** The average overall latency of an MSHR miss. */
464 Stats::Formula overallAvgMshrUncacheableLatency;
465
466 /** The number of times a thread hit its MSHR cap. */
467 Stats::Vector mshr_cap_events;
468 /** The number of times software prefetches caused the MSHR to block. */
469 Stats::Vector soft_prefetch_mshr_full;
470
471 Stats::Scalar mshr_no_allocate_misses;
472
473 /**
474 * @}
475 */
476
477 /**
478 * Register stats for this object.
479 */
480 virtual void regStats();
481
482 public:
483 typedef BaseCacheParams Params;
484 BaseCache(const Params *p);
485 ~BaseCache() {}
486
487 virtual void init();
488
489 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
490 PortID idx = InvalidPortID);
491 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
492 PortID idx = InvalidPortID);
493
494 /**
495 * Query block size of a cache.
496 * @return The block size
497 */
498 unsigned
499 getBlockSize() const
500 {
501 return blkSize;
502 }
503
504
505 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
506
507
508 const AddrRangeList &getAddrRanges() const { return addrRanges; }
509
510 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
511 {
512 return allocateBufferInternal(&mshrQueue,
513 blockAlign(pkt->getAddr()), blkSize,
514 pkt, time, requestBus);
515 }
516
517 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
518 {
519 assert(pkt->isWrite() && !pkt->isRead());
520 return allocateBufferInternal(&writeBuffer,
521 blockAlign(pkt->getAddr()), blkSize,
522 pkt, time, requestBus);
523 }
524
525 /**
526 * Returns true if the cache is blocked for accesses.
527 */
528 bool isBlocked() const
529 {
530 return blocked != 0;
531 }
532
533 /**
534 * Marks the access path of the cache as blocked for the given cause. This
535 * also sets the blocked flag in the slave interface.
536 * @param cause The reason for the cache blocking.
537 */
538 void setBlocked(BlockedCause cause)
539 {
540 uint8_t flag = 1 << cause;
541 if (blocked == 0) {
542 blocked_causes[cause]++;
543 blockedCycle = curCycle();
544 cpuSidePort->setBlocked();
545 }
546 blocked |= flag;
547 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
548 }
549
550 /**
551 * Marks the cache as unblocked for the given cause. This also clears the
552 * blocked flags in the appropriate interfaces.
553 * @param cause The newly unblocked cause.
554 * @warning Calling this function can cause a blocked request on the bus to
555 * access the cache. The cache must be in a state to handle that request.
556 */
557 void clearBlocked(BlockedCause cause)
558 {
559 uint8_t flag = 1 << cause;
560 blocked &= ~flag;
561 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
562 if (blocked == 0) {
563 blocked_cycles[cause] += curCycle() - blockedCycle;
564 cpuSidePort->clearBlocked();
565 }
566 }
567
568 /**
569 * Request the master bus for the given cause and time.
570 * @param cause The reason for the request.
571 * @param time The time to make the request.
572 */
573 void requestMemSideBus(RequestCause cause, Tick time)
574 {
575 memSidePort->requestBus(cause, time);
576 }
577
578 /**
579 * Clear the master bus request for the given cause.
580 * @param cause The request reason to clear.
581 */
582 void deassertMemSideBusRequest(RequestCause cause)
583 {
584 // Obsolete... we no longer signal bus requests explicitly so
585 // we can't deassert them. Leaving this in as a no-op since
586 // the prefetcher calls it to indicate that it no longer wants
587 // to request a prefetch, and someday that might be
588 // interesting again.
589 }
590
591 virtual unsigned int drain(DrainManager *dm);
592
593 virtual bool inCache(Addr addr, bool is_secure) const = 0;
594
595 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
596
597 void incMissCount(PacketPtr pkt)
598 {
599 assert(pkt->req->masterId() < system->maxMasters());
600 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
601 pkt->req->incAccessDepth();
602 if (missCount) {
603 --missCount;
604 if (missCount == 0)
605 exitSimLoop("A cache reached the maximum miss count");
606 }
607 }
608 void incHitCount(PacketPtr pkt)
609 {
610 assert(pkt->req->masterId() < system->maxMasters());
611 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
612
613 }
614
615};
616
617#endif //__BASE_CACHE_HH__
|