1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 215 unchanged lines hidden (view full) --- 224 } 225 226 /** Block size of this cache */ 227 const unsigned blkSize; 228 229 /** 230 * The latency of a hit in this device. 231 */ |
232 const Cycles hitLatency; |
233 234 /** 235 * The latency of sending reponse to its upper level cache/core on a 236 * linefill. In most contemporary processors, the return path on a cache 237 * miss is much quicker that the hit latency. The responseLatency parameter 238 * tries to capture this latency. 239 */ |
240 const Cycles responseLatency; |
241 242 /** The number of targets for each MSHR. */ 243 const int numTarget; 244 245 /** Do we forward snoops from mem side port through to cpu side port? */ 246 bool forwardSnoops; 247 248 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should --- 6 unchanged lines hidden (view full) --- 255 * @sa #BlockedCause 256 */ 257 uint8_t blocked; 258 259 /** Increasing order number assigned to each incoming request. */ 260 uint64_t order; 261 262 /** Stores time the cache blocked for statistics. */ |
263 Cycles blockedCycle; |
264 265 /** Pointer to the MSHR that has no targets. */ 266 MSHR *noTargetMSHR; 267 268 /** The number of misses to trigger an exit event. */ 269 Counter missCount; 270 271 /** The drain event. */ --- 215 unchanged lines hidden (view full) --- 487 * also sets the blocked flag in the slave interface. 488 * @param cause The reason for the cache blocking. 489 */ 490 void setBlocked(BlockedCause cause) 491 { 492 uint8_t flag = 1 << cause; 493 if (blocked == 0) { 494 blocked_causes[cause]++; |
495 blockedCycle = curCycle(); |
496 cpuSidePort->setBlocked(); 497 } 498 blocked |= flag; 499 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 500 } 501 502 /** 503 * Marks the cache as unblocked for the given cause. This also clears the 504 * blocked flags in the appropriate interfaces. 505 * @param cause The newly unblocked cause. 506 * @warning Calling this function can cause a blocked request on the bus to 507 * access the cache. The cache must be in a state to handle that request. 508 */ 509 void clearBlocked(BlockedCause cause) 510 { 511 uint8_t flag = 1 << cause; 512 blocked &= ~flag; 513 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 514 if (blocked == 0) { |
515 blocked_cycles[cause] += curCycle() - blockedCycle; |
516 cpuSidePort->clearBlocked(); 517 } 518 } 519 520 /** 521 * Request the master bus for the given cause and time. 522 * @param cause The reason for the request. 523 * @param time The time to make the request. --- 46 unchanged lines hidden --- |