1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 120 unchanged lines hidden (view full) --- 129 * responses outstanding. 130 */ 131 void requestBus(RequestCause cause, Tick time) 132 { 133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 134 queue.schedSendEvent(time); 135 } 136 |
137 protected: 138 139 CacheMasterPort(const std::string &_name, BaseCache *_cache, 140 MasterPacketQueue &_queue) : 141 QueuedMasterPort(_name, _cache, _queue) 142 { } 143 144 /** --- 18 unchanged lines hidden (view full) --- 163 public: 164 165 /** Do not accept any new requests. */ 166 void setBlocked(); 167 168 /** Return to normal operation and accept new requests. */ 169 void clearBlocked(); 170 |
171 protected: 172 173 CacheSlavePort(const std::string &_name, BaseCache *_cache, 174 const std::string &_label); 175 176 /** A normal packet queue used to store responses. */ 177 SlavePacketQueue queue; 178 --- 383 unchanged lines hidden --- |