1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 134 unchanged lines hidden (view full) --- 143 */ 144 void respond(PacketPtr pkt, Tick time) { 145 queue.schedSendTiming(pkt, time, true); 146 } 147 148 protected: 149 150 CacheMasterPort(const std::string &_name, BaseCache *_cache, |
151 MasterPacketQueue &_queue) : |
152 QueuedMasterPort(_name, _cache, _queue) 153 { } 154 155 /** 156 * Memory-side port always snoops. 157 * 158 * @return always true 159 */ --- 31 unchanged lines hidden (view full) --- 191 } 192 193 protected: 194 195 CacheSlavePort(const std::string &_name, BaseCache *_cache, 196 const std::string &_label); 197 198 /** A normal packet queue used to store responses. */ |
199 SlavePacketQueue queue; |
200 201 bool blocked; 202 203 bool mustSendRetry; 204 205 private: 206 207 EventWrapper<Port, &Port::sendRetry> sendRetryEvent; --- 376 unchanged lines hidden --- |