1/* |
2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright --- 82 unchanged lines hidden (view full) --- 104 Request_MSHR = MSHRQueue_MSHRs, 105 Request_WB = MSHRQueue_WriteBuffer, 106 Request_PF, 107 NUM_REQUEST_CAUSES 108 }; 109 110 protected: 111 |
112 /** 113 * A cache master port is used for the memory-side port of the 114 * cache, and in addition to the basic timing port that only sends 115 * response packets through a transmit list, it also offers the 116 * ability to schedule and send request packets (requests & 117 * writebacks). The send event is scheduled through requestBus, 118 * and the sendDeferredPacket of the timing port is modified to 119 * consider both the transmit list and the requests from the MSHR. 120 */ 121 class CacheMasterPort : public SimpleTimingPort |
122 { |
123 |
124 public: |
125 |
126 /** 127 * Schedule a send of a request packet (from the MSHR). Note 128 * that we could already have a retry or a transmit list of 129 * responses outstanding. 130 */ 131 void requestBus(RequestCause cause, Tick time) 132 { 133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 134 schedSendEvent(time); 135 } |
136 |
137 void respond(PacketPtr pkt, Tick time) { 138 schedSendTiming(pkt, time); 139 } |
140 |
141 protected: |
142 |
143 CacheMasterPort(const std::string &_name, BaseCache *_cache, 144 const std::string &_label); |
145 |
146 /** 147 * Memory-side port always snoops. 148 * 149 * return always true 150 */ 151 virtual bool isSnooping() { return true; } 152 }; |
153 |
154 /** 155 * A cache slave port is used for the CPU-side port of the cache, 156 * and it is basically a simple timing port that uses a transmit 157 * list for responses to the CPU (or connected master). In 158 * addition, it has the functionality to block the port for 159 * incoming requests. If blocked, the port will issue a retry once 160 * unblocked. 161 */ 162 class CacheSlavePort : public SimpleTimingPort 163 { 164 |
165 public: |
166 167 /** Do not accept any new requests. */ |
168 void setBlocked(); 169 |
170 /** Return to normal operation and accept new requests. */ |
171 void clearBlocked(); 172 |
173 void respond(PacketPtr pkt, Tick time) { 174 schedSendTiming(pkt, time); 175 } |
176 |
177 protected: 178 179 CacheSlavePort(const std::string &_name, BaseCache *_cache, 180 const std::string &_label); 181 |
182 bool blocked; 183 184 bool mustSendRetry; 185 |
186 private: |
187 |
188 EventWrapper<Port, &Port::sendRetry> sendRetryEvent; 189 |
190 }; 191 |
192 CacheSlavePort *cpuSidePort; 193 CacheMasterPort *memSidePort; |
194 195 protected: 196 197 /** Miss status registers */ 198 MSHRQueue mshrQueue; 199 200 /** Write/writeback buffer */ 201 MSHRQueue writeBuffer; --- 360 unchanged lines hidden --- |