1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52#include "debug/CachePort.hh"
53#include "mem/cache/mshr_queue.hh"
54#include "mem/mem_object.hh"
55#include "mem/packet.hh"
56#include "mem/request.hh"
57#include "mem/tport.hh"
58#include "params/BaseCache.hh"
59#include "sim/eventq.hh"
60#include "sim/full_system.hh"
61#include "sim/sim_exit.hh"
62
63class MSHR;
64/**
65 * A basic cache interface. Implements some common functions for speed.
66 */
67class BaseCache : public MemObject
68{
69 /**
70 * Indexes to enumerate the MSHR queues.
71 */
72 enum MSHRQueueIndex {
73 MSHRQueue_MSHRs,
74 MSHRQueue_WriteBuffer
75 };
76
76 public:
77 /**
78 * Reasons for caches to be blocked.
79 */
80 enum BlockedCause {
81 Blocked_NoMSHRs = MSHRQueue_MSHRs,
82 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
83 Blocked_NoTargets,
84 NUM_BLOCKED_CAUSES
85 };
86
87 public:
88 /**
89 * Reasons for cache to request a bus.
90 */
91 enum RequestCause {
92 Request_MSHR = MSHRQueue_MSHRs,
93 Request_WB = MSHRQueue_WriteBuffer,
94 Request_PF,
95 NUM_REQUEST_CAUSES
96 };
97
97 protected:
98 private:
99
100 class CachePort : public SimpleTimingPort
101 {
102 public:
103 BaseCache *cache;
104
105 protected:
106 CachePort(const std::string &_name, BaseCache *_cache,
107 const std::string &_label);
108
109 virtual void recvStatusChange(Status status);
110
111 virtual unsigned deviceBlockSize() const;
112
113 bool recvRetryCommon();
114
115 typedef EventWrapper<Port, &Port::sendRetry>
116 SendRetryEvent;
117
118 const std::string label;
119
120 public:
121 void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; }
122
123 void setBlocked();
124
125 void clearBlocked();
126
127 bool checkFunctional(PacketPtr pkt);
128
129 CachePort *otherPort;
130
131 bool blocked;
132
133 bool mustSendRetry;
134
135 void requestBus(RequestCause cause, Tick time)
136 {
137 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
138 if (!waitingOnRetry) {
139 schedSendEvent(time);
140 }
141 }
142
143 void respond(PacketPtr pkt, Tick time) {
144 schedSendTiming(pkt, time);
145 }
146 };
147
148 public: //Made public so coherence can get at it.
149 CachePort *cpuSidePort;
150 CachePort *memSidePort;
151
152 protected:
153
154 /** Miss status registers */
155 MSHRQueue mshrQueue;
156

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501
502 if (pkt->cmd == MemCmd::Writeback) {
503 assert(id == -1);
504 misses[pkt->cmdToIndex()][0]++;
505 /* same thing for writeback hits as misses - no context id
506 * available, meanwhile writeback hit/miss stats are not used
507 * in any aggregate hit/miss calculations, so just lump them all
508 * in bucket 0 */
501#if FULL_SYSTEM
502 } else if (id == -1) {
509 } else if (FullSystem && id == -1) {
510 // Device accesses have id -1
511 // lump device accesses into their own bucket
512 misses[pkt->cmdToIndex()][_numCpus]++;
506#endif
513 } else {
514 misses[pkt->cmdToIndex()][id % _numCpus]++;
515 }
516
517 if (missCount) {
518 --missCount;
519 if (missCount == 0)
520 exitSimLoop("A cache reached the maximum miss count");

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527 * them, so attributing a hit to a -1 context id is obviously a
528 * problem. I've noticed in the stats that hits are split into
529 * demand and non-demand hits - neither of which include writeback
530 * hits, so here, I'll just put the writeback hits into bucket 0
531 * since it won't mess with any other stats -hsul */
532 if (pkt->cmd == MemCmd::Writeback) {
533 assert(id == -1);
534 hits[pkt->cmdToIndex()][0]++;
529#if FULL_SYSTEM
530 } else if (id == -1) {
535 } else if (FullSystem && id == -1) {
536 // Device accesses have id -1
537 // lump device accesses into their own bucket
538 hits[pkt->cmdToIndex()][_numCpus]++;
534#endif
539 } else {
540 /* the % is necessary in case there are switch cpus */
541 hits[pkt->cmdToIndex()][id % _numCpus]++;
542 }
543 }
544
545};
546
547#endif //__BASE_CACHE_HH__