1/* 2 * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 481 unchanged lines hidden (view full) --- 490 * make recvTimingResp less cluttered. 491 */ 492 void handleUncacheableWriteResp(PacketPtr pkt); 493 494 /** 495 * Service non-deferred MSHR targets using the received response 496 * 497 * Iterates through the list of targets that can be serviced with |
498 * the current response. |
499 * 500 * @param mshr The MSHR that corresponds to the reponse 501 * @param pkt The response packet 502 * @param blk The reference block |
503 */ 504 virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt, |
505 CacheBlk *blk) = 0; |
506 507 /** 508 * Handles a response (cache line fill/write ack) from the bus. 509 * @param pkt The response packet 510 */ 511 virtual void recvTimingResp(PacketPtr pkt); 512 513 /** --- 826 unchanged lines hidden --- |