1/* |
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited |
3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 46 unchanged lines hidden (view full) --- 57 58#include "base/misc.hh" 59#include "base/statistics.hh" 60#include "base/trace.hh" 61#include "base/types.hh" 62#include "debug/Cache.hh" 63#include "debug/CachePort.hh" 64#include "mem/cache/mshr_queue.hh" |
65#include "mem/cache/write_queue.hh" |
66#include "mem/mem_object.hh" 67#include "mem/packet.hh" 68#include "mem/qport.hh" 69#include "mem/request.hh" 70#include "params/BaseCache.hh" 71#include "sim/eventq.hh" 72#include "sim/full_system.hh" 73#include "sim/sim_exit.hh" 74#include "sim/system.hh" 75 |
76/** 77 * A basic cache interface. Implements some common functions for speed. 78 */ 79class BaseCache : public MemObject 80{ |
81 protected: |
82 /** 83 * Indexes to enumerate the MSHR queues. 84 */ 85 enum MSHRQueueIndex { 86 MSHRQueue_MSHRs, 87 MSHRQueue_WriteBuffer 88 }; 89 --- 96 unchanged lines hidden (view full) --- 186 CacheMasterPort *memSidePort; 187 188 protected: 189 190 /** Miss status registers */ 191 MSHRQueue mshrQueue; 192 193 /** Write/writeback buffer */ |
194 WriteQueue writeBuffer; |
195 196 /** |
197 * Mark a request as in service (sent downstream in the memory 198 * system), effectively making this MSHR the ordering point. |
199 */ |
200 void markInService(MSHR *mshr, bool pending_modified_resp) |
201 { |
202 bool wasFull = mshrQueue.isFull(); 203 mshrQueue.markInService(mshr, pending_modified_resp); |
204 |
205 if (wasFull && !mshrQueue.isFull()) { 206 clearBlocked(Blocked_NoMSHRs); |
207 } |
208 } 209 |
210 void markInService(WriteQueueEntry *entry) |
211 { |
212 bool wasFull = writeBuffer.isFull(); 213 writeBuffer.markInService(entry); 214 215 if (wasFull && !writeBuffer.isFull()) { 216 clearBlocked(Blocked_NoWBBuffers); |
217 } 218 } 219 220 /** 221 * Determine if we should allocate on a fill or not. 222 * 223 * @param cmd Packet command being added as an MSHR target 224 * --- 264 unchanged lines hidden (view full) --- 489 490 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 491 492 493 const AddrRangeList &getAddrRanges() const { return addrRanges; } 494 495 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true) 496 { |
497 MSHR *mshr = mshrQueue.allocate(blockAlign(pkt->getAddr()), blkSize, 498 pkt, time, order++, 499 allocOnFill(pkt->cmd)); 500 501 if (mshrQueue.isFull()) { 502 setBlocked((BlockedCause)MSHRQueue_MSHRs); 503 } 504 505 if (sched_send) { 506 // schedule the send 507 schedMemSideSendEvent(time); 508 } 509 510 return mshr; |
511 } 512 |
513 void allocateWriteBuffer(PacketPtr pkt, Tick time) |
514 { 515 // should only see writes or clean evicts here 516 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict); 517 |
518 Addr blk_addr = blockAlign(pkt->getAddr()); 519 520 WriteQueueEntry *wq_entry = 521 writeBuffer.findMatch(blk_addr, pkt->isSecure()); 522 if (wq_entry && !wq_entry->inService) { 523 DPRINTF(Cache, "Potential to merge writeback %s to %#llx", 524 pkt->cmdString(), pkt->getAddr()); 525 } 526 527 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++); 528 529 if (writeBuffer.isFull()) { 530 setBlocked((BlockedCause)MSHRQueue_WriteBuffer); 531 } 532 533 // schedule the send 534 schedMemSideSendEvent(time); |
535 } 536 537 /** 538 * Returns true if the cache is blocked for accesses. 539 */ 540 bool isBlocked() const 541 { 542 return blocked != 0; --- 75 unchanged lines hidden --- |