1/* 2 * Copyright (c) 2012-2013, 2015 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 196 unchanged lines hidden (view full) --- 205 206 /** 207 * Allocate a buffer, passing the time indicating when schedule an 208 * event to the queued port to go and ask the MSHR and write queue 209 * if they have packets to send. 210 * 211 * allocateBufferInternal() function is called in: 212 * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer); |
213 * - MSHR allocateMissBuffer (miss in MSHR queue); |
214 */ 215 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 216 PacketPtr pkt, Tick time, bool requestBus) 217 { 218 // check that the address is block aligned since we rely on 219 // this in a number of places when checking for matches and 220 // overlap 221 assert(addr == blockAlign(addr)); --- 272 unchanged lines hidden (view full) --- 494 495 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); } 496 497 498 const AddrRangeList &getAddrRanges() const { return addrRanges; } 499 500 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 501 { |
502 return allocateBufferInternal(&mshrQueue, 503 blockAlign(pkt->getAddr()), blkSize, 504 pkt, time, requestBus); 505 } 506 507 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus) 508 { 509 assert(pkt->isWrite() && !pkt->isRead()); 510 return allocateBufferInternal(&writeBuffer, 511 blockAlign(pkt->getAddr()), blkSize, 512 pkt, time, requestBus); 513 } 514 |
515 /** 516 * Returns true if the cache is blocked for accesses. 517 */ 518 bool isBlocked() const 519 { 520 return blocked != 0; 521 } 522 --- 85 unchanged lines hidden --- |