1/* |
2 * Copyright (c) 2012-2013, 2015 ARM Limited |
3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated --- 186 unchanged lines hidden (view full) --- 197 protected: 198 199 /** Miss status registers */ 200 MSHRQueue mshrQueue; 201 202 /** Write/writeback buffer */ 203 MSHRQueue writeBuffer; 204 |
205 /** 206 * Allocate a buffer, passing the time indicating when schedule an 207 * event to the queued port to go and ask the MSHR and write queue 208 * if they have packets to send. 209 * 210 * allocateBufferInternal() function is called in: 211 * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer); 212 * - MSHR allocateMissBuffer (cacheable miss in MSHR queue); 213 * - MSHR allocateUncachedReadBuffer (unchached read allocated in MSHR 214 * queue) 215 */ |
216 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size, 217 PacketPtr pkt, Tick time, bool requestBus) 218 { 219 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++); 220 221 if (mq->isFull()) { 222 setBlocked((BlockedCause)mq->index); 223 } --- 33 unchanged lines hidden (view full) --- 257 * \return true if at least one block is dirty, false otherwise. 258 */ 259 virtual bool isDirty() const = 0; 260 261 /** Block size of this cache */ 262 const unsigned blkSize; 263 264 /** |
265 * The latency of tag lookup of a cache. It occurs when there is 266 * an access to the cache. |
267 */ |
268 const Cycles lookupLatency; |
269 270 /** |
271 * This is the forward latency of the cache. It occurs when there 272 * is a cache miss and a request is forwarded downstream, in 273 * particular an outbound miss. |
274 */ |
275 const Cycles forwardLatency; 276 277 /** The latency to fill a cache block */ 278 const Cycles fillLatency; 279 280 /** 281 * The latency of sending reponse to its upper level cache/core on 282 * a linefill. The responseLatency parameter captures this 283 * latency. 284 */ |
285 const Cycles responseLatency; 286 287 /** The number of targets for each MSHR. */ 288 const int numTarget; 289 290 /** Do we forward snoops from mem side port through to cpu side port? */ 291 const bool forwardSnoops; 292 --- 321 unchanged lines hidden --- |