1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 Blocked_PendingWriteInvalidate,
98 NUM_BLOCKED_CAUSES
99 };
100
101 /**
102 * Reasons for cache to request a bus.
103 */
104 enum RequestCause {
105 Request_MSHR = MSHRQueue_MSHRs,

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164 public:
165
166 /** Do not accept any new requests. */
167 void setBlocked();
168
169 /** Return to normal operation and accept new requests. */
170 void clearBlocked();
171
172 bool isBlocked() const { return blocked; }
173
174 protected:
175
176 CacheSlavePort(const std::string &_name, BaseCache *_cache,
177 const std::string &_label);
178
179 /** A normal packet queue used to store responses. */
180 SlavePacketQueue queue;
181

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