1a2,13
> * Copyright (c) 2012 ARM Limited
> * All rights reserved.
> *
> * The license below extends only to copyright in the software and shall
> * not be construed as granting a license to any other intellectual
> * property including but not limited to intellectual property relating
> * to a hardware implementation of the functionality of the software
> * licensed hereunder. You may use the software subject to the license
> * terms below provided that you ensure that this notice is replicated
> * unmodified and in its entirety in all distributions of the software,
> * modified or unmodified, in source code or in binary form.
> *
100c112,121
< class CachePort : public SimpleTimingPort
---
> /**
> * A cache master port is used for the memory-side port of the
> * cache, and in addition to the basic timing port that only sends
> * response packets through a transmit list, it also offers the
> * ability to schedule and send request packets (requests &
> * writebacks). The send event is scheduled through requestBus,
> * and the sendDeferredPacket of the timing port is modified to
> * consider both the transmit list and the requests from the MSHR.
> */
> class CacheMasterPort : public SimpleTimingPort
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>
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< BaseCache *cache;
105,107c126,135
< protected:
< CachePort(const std::string &_name, BaseCache *_cache,
< const std::string &_label);
---
> /**
> * Schedule a send of a request packet (from the MSHR). Note
> * that we could already have a retry or a transmit list of
> * responses outstanding.
> */
> void requestBus(RequestCause cause, Tick time)
> {
> DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
> schedSendEvent(time);
> }
109c137,139
< virtual unsigned deviceBlockSize() const;
---
> void respond(PacketPtr pkt, Tick time) {
> schedSendTiming(pkt, time);
> }
111c141
< bool recvRetryCommon();
---
> protected:
113,114c143,144
< typedef EventWrapper<Port, &Port::sendRetry>
< SendRetryEvent;
---
> CacheMasterPort(const std::string &_name, BaseCache *_cache,
> const std::string &_label);
116c146,152
< const std::string label;
---
> /**
> * Memory-side port always snoops.
> *
> * return always true
> */
> virtual bool isSnooping() { return true; }
> };
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> /**
> * A cache slave port is used for the CPU-side port of the cache,
> * and it is basically a simple timing port that uses a transmit
> * list for responses to the CPU (or connected master). In
> * addition, it has the functionality to block the port for
> * incoming requests. If blocked, the port will issue a retry once
> * unblocked.
> */
> class CacheSlavePort : public SimpleTimingPort
> {
>
118a166,167
>
> /** Do not accept any new requests. */
120a170
> /** Return to normal operation and accept new requests. */
123c173,175
< bool checkFunctional(PacketPtr pkt);
---
> void respond(PacketPtr pkt, Tick time) {
> schedSendTiming(pkt, time);
> }
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> protected:
>
> CacheSlavePort(const std::string &_name, BaseCache *_cache,
> const std::string &_label);
>
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< void requestBus(RequestCause cause, Tick time)
< {
< DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
< if (!waitingOnRetry) {
< schedSendEvent(time);
< }
< }
---
> private:
137,139c188,189
< void respond(PacketPtr pkt, Tick time) {
< schedSendTiming(pkt, time);
< }
---
> EventWrapper<Port, &Port::sendRetry> sendRetryEvent;
>
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< CachePort *cpuSidePort;
< CachePort *memSidePort;
---
> CacheSlavePort *cpuSidePort;
> CacheMasterPort *memSidePort;