2c2
< * Copyright (c) 2012-2013, 2015-2016 ARM Limited
---
> * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
42a43,44
> * Andreas Hansson
> * Nikos Nikoleris
53,54c55,56
< #include <algorithm>
< #include <list>
---
> #include <cassert>
> #include <cstdint>
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< #include <vector>
58c59
< #include "base/logging.hh"
---
> #include "base/addr_range.hh"
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> #include "enums/Clusivity.hh"
> #include "mem/cache/blk.hh"
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> #include "mem/cache/tags/base.hh"
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> #include "mem/cache/write_queue_entry.hh"
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> #include "mem/packet_queue.hh"
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< #include "params/BaseCache.hh"
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< #include "sim/full_system.hh"
---
> #include "sim/serialize.hh"
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> class BaseMasterPort;
> class BasePrefetcher;
> class BaseSlavePort;
> class MSHR;
> class MasterPort;
> class QueueEntry;
> struct BaseCacheParams;
>
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> * Override the default behaviour of sendDeferredPacket to enable
> * the memory-side cache port to also send requests based on the
> * current MSHR status. This queue has a pointer to our specific
> * cache implementation and is used by the MemSidePort.
> */
> class CacheReqPacketQueue : public ReqPacketQueue
> {
>
> protected:
>
> BaseCache &cache;
> SnoopRespPacketQueue &snoopRespQueue;
>
> public:
>
> CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
> SnoopRespPacketQueue &snoop_resp_queue,
> const std::string &label) :
> ReqPacketQueue(cache, port, label), cache(cache),
> snoopRespQueue(snoop_resp_queue) { }
>
> /**
> * Override the normal sendDeferredPacket and do not only
> * consider the transmit list (used for responses), but also
> * requests.
> */
> virtual void sendDeferredPacket();
>
> /**
> * Check if there is a conflicting snoop response about to be
> * send out, and if so simply stall any requests, and schedule
> * a send event at the same time as the next snoop response is
> * being sent out.
> */
> bool checkConflictingSnoop(Addr addr)
> {
> if (snoopRespQueue.hasAddr(addr)) {
> DPRINTF(CachePort, "Waiting for snoop response to be "
> "sent\n");
> Tick when = snoopRespQueue.deferredPacketReadyTime();
> schedSendEvent(when);
> return true;
> }
> return false;
> }
> };
>
>
> /**
> * The memory-side port extends the base cache master port with
> * access functions for functional, atomic and timing snoops.
> */
> class MemSidePort : public CacheMasterPort
> {
> private:
>
> /** The cache-specific queue. */
> CacheReqPacketQueue _reqQueue;
>
> SnoopRespPacketQueue _snoopRespQueue;
>
> // a pointer to our specific cache implementation
> BaseCache *cache;
>
> protected:
>
> virtual void recvTimingSnoopReq(PacketPtr pkt);
>
> virtual bool recvTimingResp(PacketPtr pkt);
>
> virtual Tick recvAtomicSnoop(PacketPtr pkt);
>
> virtual void recvFunctionalSnoop(PacketPtr pkt);
>
> public:
>
> MemSidePort(const std::string &_name, BaseCache *_cache,
> const std::string &_label);
> };
>
> /**
184,185c278,284
< CacheSlavePort *cpuSidePort;
< CacheMasterPort *memSidePort;
---
> /**
> * The CPU-side port extends the base cache slave port with access
> * functions for functional, atomic and timing requests.
> */
> class CpuSidePort : public CacheSlavePort
> {
> private:
186a286,311
> // a pointer to our specific cache implementation
> BaseCache *cache;
>
> protected:
> virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
>
> virtual bool tryTiming(PacketPtr pkt) override;
>
> virtual bool recvTimingReq(PacketPtr pkt) override;
>
> virtual Tick recvAtomic(PacketPtr pkt) override;
>
> virtual void recvFunctional(PacketPtr pkt) override;
>
> virtual AddrRangeList getAddrRanges() const override;
>
> public:
>
> CpuSidePort(const std::string &_name, BaseCache *_cache,
> const std::string &_label);
>
> };
>
> CpuSidePort cpuSidePort;
> MemSidePort memSidePort;
>
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> /** Tag and data Storage */
> BaseTags *tags;
>
> /** Prefetcher */
> BasePrefetcher *prefetcher;
>
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> * Notify the prefetcher on every access, not just misses.
> */
> const bool prefetchOnAccess;
>
> /**
> * Temporary cache block for occasional transitory use. We use
> * the tempBlock to fill when allocation fails (e.g., when there
> * is an outstanding request that accesses the victim block) or
> * when we want to avoid allocation (e.g., exclusive caches)
> */
> CacheBlk *tempBlock;
>
> /**
> * Upstream caches need this packet until true is returned, so
> * hold it for deletion until a subsequent call
> */
> std::unique_ptr<Packet> pendingDelete;
>
> /**
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< * Determine if we should allocate on a fill or not.
---
> * Determine whether we should allocate on a fill or not. If this
> * cache is mostly inclusive with regards to the upstream cache(s)
> * we always allocate (for any non-forwarded and cacheable
> * requests). In the case of a mostly exclusive cache, we allocate
> * on fill if the packet did not come from a cache, thus if we:
> * are dealing with a whole-line write (the latter behaves much
> * like a writeback), the original target packet came from a
> * non-caching source, or if we are performing a prefetch or LLSC.
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< * @param cmd Packet command being added as an MSHR target
---
> * @param cmd Command of the incoming requesting packet
> * @return Whether we should allocate on the fill
> */
> inline bool allocOnFill(MemCmd cmd) const
> {
> return clusivity == Enums::mostly_incl ||
> cmd == MemCmd::WriteLineReq ||
> cmd == MemCmd::ReadReq ||
> cmd == MemCmd::WriteReq ||
> cmd.isPrefetch() ||
> cmd.isLLSC();
> }
>
> /**
> * Does all the processing necessary to perform the provided request.
> * @param pkt The memory request to perform.
> * @param blk The cache block to be updated.
> * @param lat The latency of the access.
> * @param writebacks List for any writebacks that need to be performed.
> * @return Boolean indicating whether the request was satisfied.
> */
> virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
> PacketList &writebacks);
>
> /*
> * Handle a timing request that hit in the cache
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< * @return Whether we should allocate on a fill or not
---
> * @param ptk The request packet
> * @param blk The referenced block
> * @param request_time The tick at which the block lookup is compete
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< virtual bool allocOnFill(MemCmd cmd) const = 0;
---
> virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
> Tick request_time);
227a413,441
> /*
> * Handle a timing request that missed in the cache
> *
> * Implementation specific handling for different cache
> * implementations
> *
> * @param ptk The request packet
> * @param blk The referenced block
> * @param forward_time The tick at which we can process dependent requests
> * @param request_time The tick at which the block lookup is compete
> */
> virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
> Tick forward_time,
> Tick request_time) = 0;
>
> /*
> * Handle a timing request that missed in the cache
> *
> * Common functionality across different cache implementations
> *
> * @param ptk The request packet
> * @param blk The referenced block
> * @param mshr Any existing mshr for the referenced cache block
> * @param forward_time The tick at which we can process dependent requests
> * @param request_time The tick at which the block lookup is compete
> */
> void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
> Tick forward_time, Tick request_time);
>
228a443,708
> * Performs the access specified by the request.
> * @param pkt The request to perform.
> */
> virtual void recvTimingReq(PacketPtr pkt);
>
> /**
> * Handling the special case of uncacheable write responses to
> * make recvTimingResp less cluttered.
> */
> void handleUncacheableWriteResp(PacketPtr pkt);
>
> /**
> * Service non-deferred MSHR targets using the received response
> *
> * Iterates through the list of targets that can be serviced with
> * the current response. Any writebacks that need to performed
> * must be appended to the writebacks parameter.
> *
> * @param mshr The MSHR that corresponds to the reponse
> * @param pkt The response packet
> * @param blk The reference block
> * @param writebacks List of writebacks that need to be performed
> */
> virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
> CacheBlk *blk, PacketList& writebacks) = 0;
>
> /**
> * Handles a response (cache line fill/write ack) from the bus.
> * @param pkt The response packet
> */
> virtual void recvTimingResp(PacketPtr pkt);
>
> /**
> * Snoops bus transactions to maintain coherence.
> * @param pkt The current bus transaction.
> */
> virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
>
> /**
> * Handle a snoop response.
> * @param pkt Snoop response packet
> */
> virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
>
> /**
> * Handle a request in atomic mode that missed in this cache
> *
> * Creates a downstream request, sends it to the memory below and
> * handles the response. As we are in atomic mode all operations
> * are performed immediately.
> *
> * @param pkt The packet with the requests
> * @param blk The referenced block
> * @param writebacks A list with packets for any performed writebacks
> * @return Cycles for handling the request
> */
> virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
> PacketList &writebacks) = 0;
>
> /**
> * Performs the access specified by the request.
> * @param pkt The request to perform.
> * @return The number of ticks required for the access.
> */
> virtual Tick recvAtomic(PacketPtr pkt);
>
> /**
> * Snoop for the provided request in the cache and return the estimated
> * time taken.
> * @param pkt The memory request to snoop
> * @return The number of ticks required for the snoop.
> */
> virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
>
> /**
> * Performs the access specified by the request.
> *
> * @param pkt The request to perform.
> * @param fromCpuSide from the CPU side port or the memory side port
> */
> virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
>
> /**
> * Handle doing the Compare and Swap function for SPARC.
> */
> void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
>
> /**
> * Return the next queue entry to service, either a pending miss
> * from the MSHR queue, a buffered write from the write buffer, or
> * something from the prefetcher. This function is responsible
> * for prioritizing among those sources on the fly.
> */
> QueueEntry* getNextQueueEntry();
>
> /**
> * Insert writebacks into the write buffer
> */
> virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;
>
> /**
> * Send writebacks down the memory hierarchy in atomic mode
> */
> virtual void doWritebacksAtomic(PacketList& writebacks) = 0;
>
> /**
> * Create an appropriate downstream bus request packet.
> *
> * Creates a new packet with the request to be send to the memory
> * below, or nullptr if the current request in cpu_pkt should just
> * be forwarded on.
> *
> * @param cpu_pkt The miss packet that needs to be satisfied.
> * @param blk The referenced block, can be nullptr.
> * @param needs_writable Indicates that the block must be writable
> * even if the request in cpu_pkt doesn't indicate that.
> * @return A packet send to the memory below
> */
> virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
> bool needs_writable) const = 0;
>
> /**
> * Determine if clean lines should be written back or not. In
> * cases where a downstream cache is mostly inclusive we likely
> * want it to act as a victim cache also for lines that have not
> * been modified. Hence, we cannot simply drop the line (or send a
> * clean evict), but rather need to send the actual data.
> */
> const bool writebackClean;
>
> /**
> * Writebacks from the tempBlock, resulting on the response path
> * in atomic mode, must happen after the call to recvAtomic has
> * finished (for the right ordering of the packets). We therefore
> * need to hold on to the packets, and have a method and an event
> * to send them.
> */
> PacketPtr tempBlockWriteback;
>
> /**
> * Send the outstanding tempBlock writeback. To be called after
> * recvAtomic finishes in cases where the block we filled is in
> * fact the tempBlock, and now needs to be written back.
> */
> void writebackTempBlockAtomic() {
> assert(tempBlockWriteback != nullptr);
> PacketList writebacks{tempBlockWriteback};
> doWritebacksAtomic(writebacks);
> tempBlockWriteback = nullptr;
> }
>
> /**
> * An event to writeback the tempBlock after recvAtomic
> * finishes. To avoid other calls to recvAtomic getting in
> * between, we create this event with a higher priority.
> */
> EventFunctionWrapper writebackTempBlockAtomicEvent;
>
> /**
> * Perform any necessary updates to the block and perform any data
> * exchange between the packet and the block. The flags of the
> * packet are also set accordingly.
> *
> * @param pkt Request packet from upstream that hit a block
> * @param blk Cache block that the packet hit
> * @param deferred_response Whether this request originally missed
> * @param pending_downgrade Whether the writable flag is to be removed
> */
> virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
> bool deferred_response = false,
> bool pending_downgrade = false);
>
> /**
> * Maintain the clusivity of this cache by potentially
> * invalidating a block. This method works in conjunction with
> * satisfyRequest, but is separate to allow us to handle all MSHR
> * targets before potentially dropping a block.
> *
> * @param from_cache Whether we have dealt with a packet from a cache
> * @param blk The block that should potentially be dropped
> */
> void maintainClusivity(bool from_cache, CacheBlk *blk);
>
> /**
> * Handle a fill operation caused by a received packet.
> *
> * Populates a cache block and handles all outstanding requests for the
> * satisfied fill request. This version takes two memory requests. One
> * contains the fill data, the other is an optional target to satisfy.
> * Note that the reason we return a list of writebacks rather than
> * inserting them directly in the write buffer is that this function
> * is called by both atomic and timing-mode accesses, and in atomic
> * mode we don't mess with the write buffer (we just perform the
> * writebacks atomically once the original request is complete).
> *
> * @param pkt The memory request with the fill data.
> * @param blk The cache block if it already exists.
> * @param writebacks List for any writebacks that need to be performed.
> * @param allocate Whether to allocate a block or use the temp block
> * @return Pointer to the new cache block.
> */
> CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
> PacketList &writebacks, bool allocate);
>
> /**
> * Allocate a new block and perform any necessary writebacks
> *
> * Find a victim block and if necessary prepare writebacks for any
> * existing data. May return nullptr if there are no replaceable
> * blocks.
> *
> * @param addr Physical address of the new block
> * @param is_secure Set if the block should be secure
> * @param writebacks A list of writeback packets for the evicted blocks
> * @return the allocated block
> */
> CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
> /**
> * Evict a cache block.
> *
> * Performs a writeback if necesssary and invalidates the block
> *
> * @param blk Block to invalidate
> * @return A packet with the writeback, can be nullptr
> */
> M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0;
>
> /**
> * Evict a cache block.
> *
> * Performs a writeback if necesssary and invalidates the block
> *
> * @param blk Block to invalidate
> * @param writebacks Return a list of packets with writebacks
> */
> virtual void evictBlock(CacheBlk *blk, PacketList &writebacks) = 0;
>
> /**
> * Invalidate a cache block.
> *
> * @param blk Block to invalidate
> */
> void invalidateBlock(CacheBlk *blk);
>
> /**
> * Create a writeback request for the given block.
> *
> * @param blk The block to writeback.
> * @return The writeback request for the block.
> */
> PacketPtr writebackBlk(CacheBlk *blk);
>
> /**
> * Create a writeclean request for the given block.
> *
> * Creates a request that writes the block to the cache below
> * without evicting the block from the current cache.
> *
> * @param blk The block to write clean.
> * @param dest The destination of the write clean operation.
> * @param id Use the given packet id for the write clean operation.
> * @return The generated write clean packet.
> */
> PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);
>
> /**
231c711,712
< virtual void memWriteback() override = 0;
---
> virtual void memWriteback() override;
>
239c720,721
< virtual void memInvalidate() override = 0;
---
> virtual void memInvalidate() override;
>
243c725
< * \return true if at least one block is dirty, false otherwise.
---
> * @return true if at least one block is dirty, false otherwise.
245c727
< virtual bool isDirty() const = 0;
---
> bool isDirty() const;
256a739,743
> /**
> * Find next request ready time from among possible sources.
> */
> Tick nextQueueReadyTime() const;
>
295a783,789
> * Clusivity with respect to the upstream cache, determining if we
> * fill into both this cache and the cache above on a miss. Note
> * that we currently do not support strict clusivity policies.
> */
> const Enums::Clusivity clusivity;
>
> /**
466c960
< virtual void regStats() override;
---
> void regStats() override;
470c964
< ~BaseCache() {}
---
> ~BaseCache();
472c966
< virtual void init() override;
---
> void init() override;
474,477c968,971
< virtual BaseMasterPort &getMasterPort(const std::string &if_name,
< PortID idx = InvalidPortID) override;
< virtual BaseSlavePort &getSlavePort(const std::string &if_name,
< PortID idx = InvalidPortID) override;
---
> BaseMasterPort &getMasterPort(const std::string &if_name,
> PortID idx = InvalidPortID) override;
> BaseSlavePort &getSlavePort(const std::string &if_name,
> PortID idx = InvalidPortID) override;
551c1045
< cpuSidePort->setBlocked();
---
> cpuSidePort.setBlocked();
571c1065
< cpuSidePort->clearBlocked();
---
> cpuSidePort.clearBlocked();
585c1079
< memSidePort->schedSendEvent(time);
---
> memSidePort.schedSendEvent(time);
588c1082,1084
< virtual bool inCache(Addr addr, bool is_secure) const = 0;
---
> bool inCache(Addr addr, bool is_secure) const {
> return tags->findBlock(addr, is_secure);
> }
590c1086,1088
< virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
---
> bool inMissQueue(Addr addr, bool is_secure) const {
> return mshrQueue.findMatch(addr, is_secure);
> }
609a1108,1152
> /**
> * Cache block visitor that writes back dirty cache blocks using
> * functional writes.
> *
> * @return Always returns true.
> */
> bool writebackVisitor(CacheBlk &blk);
>
> /**
> * Cache block visitor that invalidates all blocks in the cache.
> *
> * @warn Dirty cache lines will not be written back to memory.
> *
> * @return Always returns true.
> */
> bool invalidateVisitor(CacheBlk &blk);
>
> /**
> * Take an MSHR, turn it into a suitable downstream packet, and
> * send it out. This construct allows a queue entry to choose a suitable
> * approach based on its type.
> *
> * @param mshr The MSHR to turn into a packet and send
> * @return True if the port is waiting for a retry
> */
> virtual bool sendMSHRQueuePacket(MSHR* mshr);
>
> /**
> * Similar to sendMSHR, but for a write-queue entry
> * instead. Create the packet, and send it, and if successful also
> * mark the entry in service.
> *
> * @param wq_entry The write-queue entry to turn into a packet and send
> * @return True if the port is waiting for a retry
> */
> bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
>
> /**
> * Serialize the state of the caches
> *
> * We currently don't support checkpointing cache state, so this panics.
> */
> void serialize(CheckpointOut &cp) const override;
> void unserialize(CheckpointIn &cp) override;
>
611a1155,1212
> /**
> * Wrap a method and present it as a cache block visitor.
> *
> * For example the forEachBlk method in the tag arrays expects a
> * callable object/function as their parameter. This class wraps a
> * method in an object and presents callable object that adheres to
> * the cache block visitor protocol.
> */
> class CacheBlkVisitorWrapper : public CacheBlkVisitor
> {
> public:
> typedef bool (BaseCache::*VisitorPtr)(CacheBlk &blk);
>
> CacheBlkVisitorWrapper(BaseCache &_cache, VisitorPtr _visitor)
> : cache(_cache), visitor(_visitor) {}
>
> bool operator()(CacheBlk &blk) override {
> return (cache.*visitor)(blk);
> }
>
> private:
> BaseCache &cache;
> VisitorPtr visitor;
> };
>
> /**
> * Cache block visitor that determines if there are dirty blocks in a
> * cache.
> *
> * Use with the forEachBlk method in the tag array to determine if the
> * array contains dirty blocks.
> */
> class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
> {
> public:
> CacheBlkIsDirtyVisitor()
> : _isDirty(false) {}
>
> bool operator()(CacheBlk &blk) override {
> if (blk.isDirty()) {
> _isDirty = true;
> return false;
> } else {
> return true;
> }
> }
>
> /**
> * Does the array contain a dirty line?
> *
> * @return true if yes, false otherwise.
> */
> bool isDirty() const { return _isDirty; };
>
> private:
> bool _isDirty;
> };
>
< * Copyright (c) 2012-2013, 2015-2016 ARM Limited
---
> * Copyright (c) 2012-2013, 2015-2016, 2018 ARM Limited
42a43,44
> * Andreas Hansson
> * Nikos Nikoleris
53,54c55,56
< #include <algorithm>
< #include <list>
---
> #include <cassert>
> #include <cstdint>
56d57
< #include <vector>
58c59
< #include "base/logging.hh"
---
> #include "base/addr_range.hh"
63a65,66
> #include "enums/Clusivity.hh"
> #include "mem/cache/blk.hh"
64a68
> #include "mem/cache/tags/base.hh"
65a70
> #include "mem/cache/write_queue_entry.hh"
67a73
> #include "mem/packet_queue.hh"
70d75
< #include "params/BaseCache.hh"
72c77
< #include "sim/full_system.hh"
---
> #include "sim/serialize.hh"
75a81,88
> class BaseMasterPort;
> class BasePrefetcher;
> class BaseSlavePort;
> class MSHR;
> class MasterPort;
> class QueueEntry;
> struct BaseCacheParams;
>
143a157,237
> * Override the default behaviour of sendDeferredPacket to enable
> * the memory-side cache port to also send requests based on the
> * current MSHR status. This queue has a pointer to our specific
> * cache implementation and is used by the MemSidePort.
> */
> class CacheReqPacketQueue : public ReqPacketQueue
> {
>
> protected:
>
> BaseCache &cache;
> SnoopRespPacketQueue &snoopRespQueue;
>
> public:
>
> CacheReqPacketQueue(BaseCache &cache, MasterPort &port,
> SnoopRespPacketQueue &snoop_resp_queue,
> const std::string &label) :
> ReqPacketQueue(cache, port, label), cache(cache),
> snoopRespQueue(snoop_resp_queue) { }
>
> /**
> * Override the normal sendDeferredPacket and do not only
> * consider the transmit list (used for responses), but also
> * requests.
> */
> virtual void sendDeferredPacket();
>
> /**
> * Check if there is a conflicting snoop response about to be
> * send out, and if so simply stall any requests, and schedule
> * a send event at the same time as the next snoop response is
> * being sent out.
> */
> bool checkConflictingSnoop(Addr addr)
> {
> if (snoopRespQueue.hasAddr(addr)) {
> DPRINTF(CachePort, "Waiting for snoop response to be "
> "sent\n");
> Tick when = snoopRespQueue.deferredPacketReadyTime();
> schedSendEvent(when);
> return true;
> }
> return false;
> }
> };
>
>
> /**
> * The memory-side port extends the base cache master port with
> * access functions for functional, atomic and timing snoops.
> */
> class MemSidePort : public CacheMasterPort
> {
> private:
>
> /** The cache-specific queue. */
> CacheReqPacketQueue _reqQueue;
>
> SnoopRespPacketQueue _snoopRespQueue;
>
> // a pointer to our specific cache implementation
> BaseCache *cache;
>
> protected:
>
> virtual void recvTimingSnoopReq(PacketPtr pkt);
>
> virtual bool recvTimingResp(PacketPtr pkt);
>
> virtual Tick recvAtomicSnoop(PacketPtr pkt);
>
> virtual void recvFunctionalSnoop(PacketPtr pkt);
>
> public:
>
> MemSidePort(const std::string &_name, BaseCache *_cache,
> const std::string &_label);
> };
>
> /**
184,185c278,284
< CacheSlavePort *cpuSidePort;
< CacheMasterPort *memSidePort;
---
> /**
> * The CPU-side port extends the base cache slave port with access
> * functions for functional, atomic and timing requests.
> */
> class CpuSidePort : public CacheSlavePort
> {
> private:
186a286,311
> // a pointer to our specific cache implementation
> BaseCache *cache;
>
> protected:
> virtual bool recvTimingSnoopResp(PacketPtr pkt) override;
>
> virtual bool tryTiming(PacketPtr pkt) override;
>
> virtual bool recvTimingReq(PacketPtr pkt) override;
>
> virtual Tick recvAtomic(PacketPtr pkt) override;
>
> virtual void recvFunctional(PacketPtr pkt) override;
>
> virtual AddrRangeList getAddrRanges() const override;
>
> public:
>
> CpuSidePort(const std::string &_name, BaseCache *_cache,
> const std::string &_label);
>
> };
>
> CpuSidePort cpuSidePort;
> MemSidePort memSidePort;
>
194a320,325
> /** Tag and data Storage */
> BaseTags *tags;
>
> /** Prefetcher */
> BasePrefetcher *prefetcher;
>
195a327,345
> * Notify the prefetcher on every access, not just misses.
> */
> const bool prefetchOnAccess;
>
> /**
> * Temporary cache block for occasional transitory use. We use
> * the tempBlock to fill when allocation fails (e.g., when there
> * is an outstanding request that accesses the victim block) or
> * when we want to avoid allocation (e.g., exclusive caches)
> */
> CacheBlk *tempBlock;
>
> /**
> * Upstream caches need this packet until true is returned, so
> * hold it for deletion until a subsequent call
> */
> std::unique_ptr<Packet> pendingDelete;
>
> /**
220c370,377
< * Determine if we should allocate on a fill or not.
---
> * Determine whether we should allocate on a fill or not. If this
> * cache is mostly inclusive with regards to the upstream cache(s)
> * we always allocate (for any non-forwarded and cacheable
> * requests). In the case of a mostly exclusive cache, we allocate
> * on fill if the packet did not come from a cache, thus if we:
> * are dealing with a whole-line write (the latter behaves much
> * like a writeback), the original target packet came from a
> * non-caching source, or if we are performing a prefetch or LLSC.
222c379,404
< * @param cmd Packet command being added as an MSHR target
---
> * @param cmd Command of the incoming requesting packet
> * @return Whether we should allocate on the fill
> */
> inline bool allocOnFill(MemCmd cmd) const
> {
> return clusivity == Enums::mostly_incl ||
> cmd == MemCmd::WriteLineReq ||
> cmd == MemCmd::ReadReq ||
> cmd == MemCmd::WriteReq ||
> cmd.isPrefetch() ||
> cmd.isLLSC();
> }
>
> /**
> * Does all the processing necessary to perform the provided request.
> * @param pkt The memory request to perform.
> * @param blk The cache block to be updated.
> * @param lat The latency of the access.
> * @param writebacks List for any writebacks that need to be performed.
> * @return Boolean indicating whether the request was satisfied.
> */
> virtual bool access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
> PacketList &writebacks);
>
> /*
> * Handle a timing request that hit in the cache
224c406,408
< * @return Whether we should allocate on a fill or not
---
> * @param ptk The request packet
> * @param blk The referenced block
> * @param request_time The tick at which the block lookup is compete
226c410,411
< virtual bool allocOnFill(MemCmd cmd) const = 0;
---
> virtual void handleTimingReqHit(PacketPtr pkt, CacheBlk *blk,
> Tick request_time);
227a413,441
> /*
> * Handle a timing request that missed in the cache
> *
> * Implementation specific handling for different cache
> * implementations
> *
> * @param ptk The request packet
> * @param blk The referenced block
> * @param forward_time The tick at which we can process dependent requests
> * @param request_time The tick at which the block lookup is compete
> */
> virtual void handleTimingReqMiss(PacketPtr pkt, CacheBlk *blk,
> Tick forward_time,
> Tick request_time) = 0;
>
> /*
> * Handle a timing request that missed in the cache
> *
> * Common functionality across different cache implementations
> *
> * @param ptk The request packet
> * @param blk The referenced block
> * @param mshr Any existing mshr for the referenced cache block
> * @param forward_time The tick at which we can process dependent requests
> * @param request_time The tick at which the block lookup is compete
> */
> void handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk,
> Tick forward_time, Tick request_time);
>
228a443,708
> * Performs the access specified by the request.
> * @param pkt The request to perform.
> */
> virtual void recvTimingReq(PacketPtr pkt);
>
> /**
> * Handling the special case of uncacheable write responses to
> * make recvTimingResp less cluttered.
> */
> void handleUncacheableWriteResp(PacketPtr pkt);
>
> /**
> * Service non-deferred MSHR targets using the received response
> *
> * Iterates through the list of targets that can be serviced with
> * the current response. Any writebacks that need to performed
> * must be appended to the writebacks parameter.
> *
> * @param mshr The MSHR that corresponds to the reponse
> * @param pkt The response packet
> * @param blk The reference block
> * @param writebacks List of writebacks that need to be performed
> */
> virtual void serviceMSHRTargets(MSHR *mshr, const PacketPtr pkt,
> CacheBlk *blk, PacketList& writebacks) = 0;
>
> /**
> * Handles a response (cache line fill/write ack) from the bus.
> * @param pkt The response packet
> */
> virtual void recvTimingResp(PacketPtr pkt);
>
> /**
> * Snoops bus transactions to maintain coherence.
> * @param pkt The current bus transaction.
> */
> virtual void recvTimingSnoopReq(PacketPtr pkt) = 0;
>
> /**
> * Handle a snoop response.
> * @param pkt Snoop response packet
> */
> virtual void recvTimingSnoopResp(PacketPtr pkt) = 0;
>
> /**
> * Handle a request in atomic mode that missed in this cache
> *
> * Creates a downstream request, sends it to the memory below and
> * handles the response. As we are in atomic mode all operations
> * are performed immediately.
> *
> * @param pkt The packet with the requests
> * @param blk The referenced block
> * @param writebacks A list with packets for any performed writebacks
> * @return Cycles for handling the request
> */
> virtual Cycles handleAtomicReqMiss(PacketPtr pkt, CacheBlk *blk,
> PacketList &writebacks) = 0;
>
> /**
> * Performs the access specified by the request.
> * @param pkt The request to perform.
> * @return The number of ticks required for the access.
> */
> virtual Tick recvAtomic(PacketPtr pkt);
>
> /**
> * Snoop for the provided request in the cache and return the estimated
> * time taken.
> * @param pkt The memory request to snoop
> * @return The number of ticks required for the snoop.
> */
> virtual Tick recvAtomicSnoop(PacketPtr pkt) = 0;
>
> /**
> * Performs the access specified by the request.
> *
> * @param pkt The request to perform.
> * @param fromCpuSide from the CPU side port or the memory side port
> */
> virtual void functionalAccess(PacketPtr pkt, bool from_cpu_side);
>
> /**
> * Handle doing the Compare and Swap function for SPARC.
> */
> void cmpAndSwap(CacheBlk *blk, PacketPtr pkt);
>
> /**
> * Return the next queue entry to service, either a pending miss
> * from the MSHR queue, a buffered write from the write buffer, or
> * something from the prefetcher. This function is responsible
> * for prioritizing among those sources on the fly.
> */
> QueueEntry* getNextQueueEntry();
>
> /**
> * Insert writebacks into the write buffer
> */
> virtual void doWritebacks(PacketList& writebacks, Tick forward_time) = 0;
>
> /**
> * Send writebacks down the memory hierarchy in atomic mode
> */
> virtual void doWritebacksAtomic(PacketList& writebacks) = 0;
>
> /**
> * Create an appropriate downstream bus request packet.
> *
> * Creates a new packet with the request to be send to the memory
> * below, or nullptr if the current request in cpu_pkt should just
> * be forwarded on.
> *
> * @param cpu_pkt The miss packet that needs to be satisfied.
> * @param blk The referenced block, can be nullptr.
> * @param needs_writable Indicates that the block must be writable
> * even if the request in cpu_pkt doesn't indicate that.
> * @return A packet send to the memory below
> */
> virtual PacketPtr createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk,
> bool needs_writable) const = 0;
>
> /**
> * Determine if clean lines should be written back or not. In
> * cases where a downstream cache is mostly inclusive we likely
> * want it to act as a victim cache also for lines that have not
> * been modified. Hence, we cannot simply drop the line (or send a
> * clean evict), but rather need to send the actual data.
> */
> const bool writebackClean;
>
> /**
> * Writebacks from the tempBlock, resulting on the response path
> * in atomic mode, must happen after the call to recvAtomic has
> * finished (for the right ordering of the packets). We therefore
> * need to hold on to the packets, and have a method and an event
> * to send them.
> */
> PacketPtr tempBlockWriteback;
>
> /**
> * Send the outstanding tempBlock writeback. To be called after
> * recvAtomic finishes in cases where the block we filled is in
> * fact the tempBlock, and now needs to be written back.
> */
> void writebackTempBlockAtomic() {
> assert(tempBlockWriteback != nullptr);
> PacketList writebacks{tempBlockWriteback};
> doWritebacksAtomic(writebacks);
> tempBlockWriteback = nullptr;
> }
>
> /**
> * An event to writeback the tempBlock after recvAtomic
> * finishes. To avoid other calls to recvAtomic getting in
> * between, we create this event with a higher priority.
> */
> EventFunctionWrapper writebackTempBlockAtomicEvent;
>
> /**
> * Perform any necessary updates to the block and perform any data
> * exchange between the packet and the block. The flags of the
> * packet are also set accordingly.
> *
> * @param pkt Request packet from upstream that hit a block
> * @param blk Cache block that the packet hit
> * @param deferred_response Whether this request originally missed
> * @param pending_downgrade Whether the writable flag is to be removed
> */
> virtual void satisfyRequest(PacketPtr pkt, CacheBlk *blk,
> bool deferred_response = false,
> bool pending_downgrade = false);
>
> /**
> * Maintain the clusivity of this cache by potentially
> * invalidating a block. This method works in conjunction with
> * satisfyRequest, but is separate to allow us to handle all MSHR
> * targets before potentially dropping a block.
> *
> * @param from_cache Whether we have dealt with a packet from a cache
> * @param blk The block that should potentially be dropped
> */
> void maintainClusivity(bool from_cache, CacheBlk *blk);
>
> /**
> * Handle a fill operation caused by a received packet.
> *
> * Populates a cache block and handles all outstanding requests for the
> * satisfied fill request. This version takes two memory requests. One
> * contains the fill data, the other is an optional target to satisfy.
> * Note that the reason we return a list of writebacks rather than
> * inserting them directly in the write buffer is that this function
> * is called by both atomic and timing-mode accesses, and in atomic
> * mode we don't mess with the write buffer (we just perform the
> * writebacks atomically once the original request is complete).
> *
> * @param pkt The memory request with the fill data.
> * @param blk The cache block if it already exists.
> * @param writebacks List for any writebacks that need to be performed.
> * @param allocate Whether to allocate a block or use the temp block
> * @return Pointer to the new cache block.
> */
> CacheBlk *handleFill(PacketPtr pkt, CacheBlk *blk,
> PacketList &writebacks, bool allocate);
>
> /**
> * Allocate a new block and perform any necessary writebacks
> *
> * Find a victim block and if necessary prepare writebacks for any
> * existing data. May return nullptr if there are no replaceable
> * blocks.
> *
> * @param addr Physical address of the new block
> * @param is_secure Set if the block should be secure
> * @param writebacks A list of writeback packets for the evicted blocks
> * @return the allocated block
> */
> CacheBlk *allocateBlock(Addr addr, bool is_secure, PacketList &writebacks);
> /**
> * Evict a cache block.
> *
> * Performs a writeback if necesssary and invalidates the block
> *
> * @param blk Block to invalidate
> * @return A packet with the writeback, can be nullptr
> */
> M5_NODISCARD virtual PacketPtr evictBlock(CacheBlk *blk) = 0;
>
> /**
> * Evict a cache block.
> *
> * Performs a writeback if necesssary and invalidates the block
> *
> * @param blk Block to invalidate
> * @param writebacks Return a list of packets with writebacks
> */
> virtual void evictBlock(CacheBlk *blk, PacketList &writebacks) = 0;
>
> /**
> * Invalidate a cache block.
> *
> * @param blk Block to invalidate
> */
> void invalidateBlock(CacheBlk *blk);
>
> /**
> * Create a writeback request for the given block.
> *
> * @param blk The block to writeback.
> * @return The writeback request for the block.
> */
> PacketPtr writebackBlk(CacheBlk *blk);
>
> /**
> * Create a writeclean request for the given block.
> *
> * Creates a request that writes the block to the cache below
> * without evicting the block from the current cache.
> *
> * @param blk The block to write clean.
> * @param dest The destination of the write clean operation.
> * @param id Use the given packet id for the write clean operation.
> * @return The generated write clean packet.
> */
> PacketPtr writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id);
>
> /**
231c711,712
< virtual void memWriteback() override = 0;
---
> virtual void memWriteback() override;
>
239c720,721
< virtual void memInvalidate() override = 0;
---
> virtual void memInvalidate() override;
>
243c725
< * \return true if at least one block is dirty, false otherwise.
---
> * @return true if at least one block is dirty, false otherwise.
245c727
< virtual bool isDirty() const = 0;
---
> bool isDirty() const;
256a739,743
> /**
> * Find next request ready time from among possible sources.
> */
> Tick nextQueueReadyTime() const;
>
295a783,789
> * Clusivity with respect to the upstream cache, determining if we
> * fill into both this cache and the cache above on a miss. Note
> * that we currently do not support strict clusivity policies.
> */
> const Enums::Clusivity clusivity;
>
> /**
466c960
< virtual void regStats() override;
---
> void regStats() override;
470c964
< ~BaseCache() {}
---
> ~BaseCache();
472c966
< virtual void init() override;
---
> void init() override;
474,477c968,971
< virtual BaseMasterPort &getMasterPort(const std::string &if_name,
< PortID idx = InvalidPortID) override;
< virtual BaseSlavePort &getSlavePort(const std::string &if_name,
< PortID idx = InvalidPortID) override;
---
> BaseMasterPort &getMasterPort(const std::string &if_name,
> PortID idx = InvalidPortID) override;
> BaseSlavePort &getSlavePort(const std::string &if_name,
> PortID idx = InvalidPortID) override;
551c1045
< cpuSidePort->setBlocked();
---
> cpuSidePort.setBlocked();
571c1065
< cpuSidePort->clearBlocked();
---
> cpuSidePort.clearBlocked();
585c1079
< memSidePort->schedSendEvent(time);
---
> memSidePort.schedSendEvent(time);
588c1082,1084
< virtual bool inCache(Addr addr, bool is_secure) const = 0;
---
> bool inCache(Addr addr, bool is_secure) const {
> return tags->findBlock(addr, is_secure);
> }
590c1086,1088
< virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
---
> bool inMissQueue(Addr addr, bool is_secure) const {
> return mshrQueue.findMatch(addr, is_secure);
> }
609a1108,1152
> /**
> * Cache block visitor that writes back dirty cache blocks using
> * functional writes.
> *
> * @return Always returns true.
> */
> bool writebackVisitor(CacheBlk &blk);
>
> /**
> * Cache block visitor that invalidates all blocks in the cache.
> *
> * @warn Dirty cache lines will not be written back to memory.
> *
> * @return Always returns true.
> */
> bool invalidateVisitor(CacheBlk &blk);
>
> /**
> * Take an MSHR, turn it into a suitable downstream packet, and
> * send it out. This construct allows a queue entry to choose a suitable
> * approach based on its type.
> *
> * @param mshr The MSHR to turn into a packet and send
> * @return True if the port is waiting for a retry
> */
> virtual bool sendMSHRQueuePacket(MSHR* mshr);
>
> /**
> * Similar to sendMSHR, but for a write-queue entry
> * instead. Create the packet, and send it, and if successful also
> * mark the entry in service.
> *
> * @param wq_entry The write-queue entry to turn into a packet and send
> * @return True if the port is waiting for a retry
> */
> bool sendWriteQueuePacket(WriteQueueEntry* wq_entry);
>
> /**
> * Serialize the state of the caches
> *
> * We currently don't support checkpointing cache state, so this panics.
> */
> void serialize(CheckpointOut &cp) const override;
> void unserialize(CheckpointIn &cp) override;
>
611a1155,1212
> /**
> * Wrap a method and present it as a cache block visitor.
> *
> * For example the forEachBlk method in the tag arrays expects a
> * callable object/function as their parameter. This class wraps a
> * method in an object and presents callable object that adheres to
> * the cache block visitor protocol.
> */
> class CacheBlkVisitorWrapper : public CacheBlkVisitor
> {
> public:
> typedef bool (BaseCache::*VisitorPtr)(CacheBlk &blk);
>
> CacheBlkVisitorWrapper(BaseCache &_cache, VisitorPtr _visitor)
> : cache(_cache), visitor(_visitor) {}
>
> bool operator()(CacheBlk &blk) override {
> return (cache.*visitor)(blk);
> }
>
> private:
> BaseCache &cache;
> VisitorPtr visitor;
> };
>
> /**
> * Cache block visitor that determines if there are dirty blocks in a
> * cache.
> *
> * Use with the forEachBlk method in the tag array to determine if the
> * array contains dirty blocks.
> */
> class CacheBlkIsDirtyVisitor : public CacheBlkVisitor
> {
> public:
> CacheBlkIsDirtyVisitor()
> : _isDirty(false) {}
>
> bool operator()(CacheBlk &blk) override {
> if (blk.isDirty()) {
> _isDirty = true;
> return false;
> } else {
> return true;
> }
> }
>
> /**
> * Does the array contain a dirty line?
> *
> * @return true if yes, false otherwise.
> */
> bool isDirty() const { return _isDirty; };
>
> private:
> bool _isDirty;
> };
>