2c2
< * Copyright (c) 2012-2013 ARM Limited
---
> * Copyright (c) 2012-2013, 2015 ARM Limited
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> /**
> * Allocate a buffer, passing the time indicating when schedule an
> * event to the queued port to go and ask the MSHR and write queue
> * if they have packets to send.
> *
> * allocateBufferInternal() function is called in:
> * - MSHR allocateWriteBuffer (unchached write forwarded to WriteBuffer);
> * - MSHR allocateMissBuffer (cacheable miss in MSHR queue);
> * - MSHR allocateUncachedReadBuffer (unchached read allocated in MSHR
> * queue)
> */
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< * The latency of a hit in this device.
---
> * The latency of tag lookup of a cache. It occurs when there is
> * an access to the cache.
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< const Cycles hitLatency;
---
> const Cycles lookupLatency;
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< * The latency of sending reponse to its upper level cache/core on a
< * linefill. In most contemporary processors, the return path on a cache
< * miss is much quicker that the hit latency. The responseLatency parameter
< * tries to capture this latency.
---
> * This is the forward latency of the cache. It occurs when there
> * is a cache miss and a request is forwarded downstream, in
> * particular an outbound miss.
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> const Cycles forwardLatency;
>
> /** The latency to fill a cache block */
> const Cycles fillLatency;
>
> /**
> * The latency of sending reponse to its upper level cache/core on
> * a linefill. The responseLatency parameter captures this
> * latency.
> */