1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
135 }
136
137 protected:
138
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 MasterPacketQueue &_queue) :
141 QueuedMasterPort(_name, _cache, _queue)
142 { }
143
144 /**
145 * Memory-side port always snoops.
146 *
147 * @return always true
148 */
149 virtual bool isSnooping() const { return true; }
150 };
151
152 /**
153 * A cache slave port is used for the CPU-side port of the cache,
154 * and it is basically a simple timing port that uses a transmit
155 * list for responses to the CPU (or connected master). In
156 * addition, it has the functionality to block the port for
157 * incoming requests. If blocked, the port will issue a retry once
158 * unblocked.
159 */
160 class CacheSlavePort : public QueuedSlavePort
161 {
162
163 public:
164
165 /** Do not accept any new requests. */
166 void setBlocked();
167
168 /** Return to normal operation and accept new requests. */
169 void clearBlocked();
170
171 protected:
172
173 CacheSlavePort(const std::string &_name, BaseCache *_cache,
174 const std::string &_label);
175
176 /** A normal packet queue used to store responses. */
177 SlavePacketQueue queue;
178
179 bool blocked;
180
181 bool mustSendRetry;
182
183 private:
184
185 EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent;
186
187 };
188
189 CacheSlavePort *cpuSidePort;
190 CacheMasterPort *memSidePort;
191
192 protected:
193
194 /** Miss status registers */
195 MSHRQueue mshrQueue;
196
197 /** Write/writeback buffer */
198 MSHRQueue writeBuffer;
199
200 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
201 PacketPtr pkt, Tick time, bool requestBus)
202 {
203 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
204
205 if (mq->isFull()) {
206 setBlocked((BlockedCause)mq->index);
207 }
208
209 if (requestBus) {
210 requestMemSideBus((RequestCause)mq->index, time);
211 }
212
213 return mshr;
214 }
215
216 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
217 {
218 MSHRQueue *mq = mshr->queue;
219 bool wasFull = mq->isFull();
220 mq->markInService(mshr, pkt);
221 if (wasFull && !mq->isFull()) {
222 clearBlocked((BlockedCause)mq->index);
223 }
224 }
225
226 /** Block size of this cache */
227 const unsigned blkSize;
228
229 /**
230 * The latency of a hit in this device.
231 */
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
135 }
136
137 protected:
138
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 MasterPacketQueue &_queue) :
141 QueuedMasterPort(_name, _cache, _queue)
142 { }
143
144 /**
145 * Memory-side port always snoops.
146 *
147 * @return always true
148 */
149 virtual bool isSnooping() const { return true; }
150 };
151
152 /**
153 * A cache slave port is used for the CPU-side port of the cache,
154 * and it is basically a simple timing port that uses a transmit
155 * list for responses to the CPU (or connected master). In
156 * addition, it has the functionality to block the port for
157 * incoming requests. If blocked, the port will issue a retry once
158 * unblocked.
159 */
160 class CacheSlavePort : public QueuedSlavePort
161 {
162
163 public:
164
165 /** Do not accept any new requests. */
166 void setBlocked();
167
168 /** Return to normal operation and accept new requests. */
169 void clearBlocked();
170
171 protected:
172
173 CacheSlavePort(const std::string &_name, BaseCache *_cache,
174 const std::string &_label);
175
176 /** A normal packet queue used to store responses. */
177 SlavePacketQueue queue;
178
179 bool blocked;
180
181 bool mustSendRetry;
182
183 private:
184
185 EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent;
186
187 };
188
189 CacheSlavePort *cpuSidePort;
190 CacheMasterPort *memSidePort;
191
192 protected:
193
194 /** Miss status registers */
195 MSHRQueue mshrQueue;
196
197 /** Write/writeback buffer */
198 MSHRQueue writeBuffer;
199
200 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
201 PacketPtr pkt, Tick time, bool requestBus)
202 {
203 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
204
205 if (mq->isFull()) {
206 setBlocked((BlockedCause)mq->index);
207 }
208
209 if (requestBus) {
210 requestMemSideBus((RequestCause)mq->index, time);
211 }
212
213 return mshr;
214 }
215
216 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
217 {
218 MSHRQueue *mq = mshr->queue;
219 bool wasFull = mq->isFull();
220 mq->markInService(mshr, pkt);
221 if (wasFull && !mq->isFull()) {
222 clearBlocked((BlockedCause)mq->index);
223 }
224 }
225
226 /** Block size of this cache */
227 const unsigned blkSize;
228
229 /**
230 * The latency of a hit in this device.
231 */
|
234 /** The number of targets for each MSHR. */
235 const int numTarget;
236
237 /** Do we forward snoops from mem side port through to cpu side port? */
238 bool forwardSnoops;
239
240 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
241 * never try to forward ownership and similar optimizations to the cpu
242 * side */
243 bool isTopLevel;
244
245 /**
246 * Bit vector of the blocking reasons for the access path.
247 * @sa #BlockedCause
248 */
249 uint8_t blocked;
250
251 /** Increasing order number assigned to each incoming request. */
252 uint64_t order;
253
254 /** Stores time the cache blocked for statistics. */
255 Tick blockedCycle;
256
257 /** Pointer to the MSHR that has no targets. */
258 MSHR *noTargetMSHR;
259
260 /** The number of misses to trigger an exit event. */
261 Counter missCount;
262
263 /** The drain event. */
264 Event *drainEvent;
265
266 /**
267 * The address range to which the cache responds on the CPU side.
268 * Normally this is all possible memory addresses. */
269 AddrRangeList addrRanges;
270
271 public:
272 /** System we are currently operating in. */
273 System *system;
274
275 // Statistics
276 /**
277 * @addtogroup CacheStatistics
278 * @{
279 */
280
281 /** Number of hits per thread for each type of command. @sa Packet::Command */
282 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
283 /** Number of hits for demand accesses. */
284 Stats::Formula demandHits;
285 /** Number of hit for all accesses. */
286 Stats::Formula overallHits;
287
288 /** Number of misses per thread for each type of command. @sa Packet::Command */
289 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
290 /** Number of misses for demand accesses. */
291 Stats::Formula demandMisses;
292 /** Number of misses for all accesses. */
293 Stats::Formula overallMisses;
294
295 /**
296 * Total number of cycles per thread/command spent waiting for a miss.
297 * Used to calculate the average miss latency.
298 */
299 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
300 /** Total number of cycles spent waiting for demand misses. */
301 Stats::Formula demandMissLatency;
302 /** Total number of cycles spent waiting for all misses. */
303 Stats::Formula overallMissLatency;
304
305 /** The number of accesses per command and thread. */
306 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
307 /** The number of demand accesses. */
308 Stats::Formula demandAccesses;
309 /** The number of overall accesses. */
310 Stats::Formula overallAccesses;
311
312 /** The miss rate per command and thread. */
313 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
314 /** The miss rate of all demand accesses. */
315 Stats::Formula demandMissRate;
316 /** The miss rate for all accesses. */
317 Stats::Formula overallMissRate;
318
319 /** The average miss latency per command and thread. */
320 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
321 /** The average miss latency for demand misses. */
322 Stats::Formula demandAvgMissLatency;
323 /** The average miss latency for all misses. */
324 Stats::Formula overallAvgMissLatency;
325
326 /** The total number of cycles blocked for each blocked cause. */
327 Stats::Vector blocked_cycles;
328 /** The number of times this cache blocked for each blocked cause. */
329 Stats::Vector blocked_causes;
330
331 /** The average number of cycles blocked for each blocked cause. */
332 Stats::Formula avg_blocked;
333
334 /** The number of fast writes (WH64) performed. */
335 Stats::Scalar fastWrites;
336
337 /** The number of cache copies performed. */
338 Stats::Scalar cacheCopies;
339
340 /** Number of blocks written back per thread. */
341 Stats::Vector writebacks;
342
343 /** Number of misses that hit in the MSHRs per command and thread. */
344 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
345 /** Demand misses that hit in the MSHRs. */
346 Stats::Formula demandMshrHits;
347 /** Total number of misses that hit in the MSHRs. */
348 Stats::Formula overallMshrHits;
349
350 /** Number of misses that miss in the MSHRs, per command and thread. */
351 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
352 /** Demand misses that miss in the MSHRs. */
353 Stats::Formula demandMshrMisses;
354 /** Total number of misses that miss in the MSHRs. */
355 Stats::Formula overallMshrMisses;
356
357 /** Number of misses that miss in the MSHRs, per command and thread. */
358 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
359 /** Total number of misses that miss in the MSHRs. */
360 Stats::Formula overallMshrUncacheable;
361
362 /** Total cycle latency of each MSHR miss, per command and thread. */
363 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
364 /** Total cycle latency of demand MSHR misses. */
365 Stats::Formula demandMshrMissLatency;
366 /** Total cycle latency of overall MSHR misses. */
367 Stats::Formula overallMshrMissLatency;
368
369 /** Total cycle latency of each MSHR miss, per command and thread. */
370 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
371 /** Total cycle latency of overall MSHR misses. */
372 Stats::Formula overallMshrUncacheableLatency;
373
374#if 0
375 /** The total number of MSHR accesses per command and thread. */
376 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
377 /** The total number of demand MSHR accesses. */
378 Stats::Formula demandMshrAccesses;
379 /** The total number of MSHR accesses. */
380 Stats::Formula overallMshrAccesses;
381#endif
382
383 /** The miss rate in the MSHRs pre command and thread. */
384 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
385 /** The demand miss rate in the MSHRs. */
386 Stats::Formula demandMshrMissRate;
387 /** The overall miss rate in the MSHRs. */
388 Stats::Formula overallMshrMissRate;
389
390 /** The average latency of an MSHR miss, per command and thread. */
391 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
392 /** The average latency of a demand MSHR miss. */
393 Stats::Formula demandAvgMshrMissLatency;
394 /** The average overall latency of an MSHR miss. */
395 Stats::Formula overallAvgMshrMissLatency;
396
397 /** The average latency of an MSHR miss, per command and thread. */
398 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
399 /** The average overall latency of an MSHR miss. */
400 Stats::Formula overallAvgMshrUncacheableLatency;
401
402 /** The number of times a thread hit its MSHR cap. */
403 Stats::Vector mshr_cap_events;
404 /** The number of times software prefetches caused the MSHR to block. */
405 Stats::Vector soft_prefetch_mshr_full;
406
407 Stats::Scalar mshr_no_allocate_misses;
408
409 /**
410 * @}
411 */
412
413 /**
414 * Register stats for this object.
415 */
416 virtual void regStats();
417
418 public:
419 typedef BaseCacheParams Params;
420 BaseCache(const Params *p);
421 ~BaseCache() {}
422
423 virtual void init();
424
425 virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
426 virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1);
427
428 /**
429 * Query block size of a cache.
430 * @return The block size
431 */
432 unsigned
433 getBlockSize() const
434 {
435 return blkSize;
436 }
437
438
439 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
440
441
442 const AddrRangeList &getAddrRanges() const { return addrRanges; }
443
444 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
445 {
446 assert(!pkt->req->isUncacheable());
447 return allocateBufferInternal(&mshrQueue,
448 blockAlign(pkt->getAddr()), blkSize,
449 pkt, time, requestBus);
450 }
451
452 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
453 {
454 assert(pkt->isWrite() && !pkt->isRead());
455 return allocateBufferInternal(&writeBuffer,
456 pkt->getAddr(), pkt->getSize(),
457 pkt, time, requestBus);
458 }
459
460 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
461 {
462 assert(pkt->req->isUncacheable());
463 assert(pkt->isRead());
464 return allocateBufferInternal(&mshrQueue,
465 pkt->getAddr(), pkt->getSize(),
466 pkt, time, requestBus);
467 }
468
469 /**
470 * Returns true if the cache is blocked for accesses.
471 */
472 bool isBlocked()
473 {
474 return blocked != 0;
475 }
476
477 /**
478 * Marks the access path of the cache as blocked for the given cause. This
479 * also sets the blocked flag in the slave interface.
480 * @param cause The reason for the cache blocking.
481 */
482 void setBlocked(BlockedCause cause)
483 {
484 uint8_t flag = 1 << cause;
485 if (blocked == 0) {
486 blocked_causes[cause]++;
487 blockedCycle = curTick();
488 cpuSidePort->setBlocked();
489 }
490 blocked |= flag;
491 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
492 }
493
494 /**
495 * Marks the cache as unblocked for the given cause. This also clears the
496 * blocked flags in the appropriate interfaces.
497 * @param cause The newly unblocked cause.
498 * @warning Calling this function can cause a blocked request on the bus to
499 * access the cache. The cache must be in a state to handle that request.
500 */
501 void clearBlocked(BlockedCause cause)
502 {
503 uint8_t flag = 1 << cause;
504 blocked &= ~flag;
505 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
506 if (blocked == 0) {
507 blocked_cycles[cause] += curTick() - blockedCycle;
508 cpuSidePort->clearBlocked();
509 }
510 }
511
512 /**
513 * Request the master bus for the given cause and time.
514 * @param cause The reason for the request.
515 * @param time The time to make the request.
516 */
517 void requestMemSideBus(RequestCause cause, Tick time)
518 {
519 memSidePort->requestBus(cause, time);
520 }
521
522 /**
523 * Clear the master bus request for the given cause.
524 * @param cause The request reason to clear.
525 */
526 void deassertMemSideBusRequest(RequestCause cause)
527 {
528 // Obsolete... we no longer signal bus requests explicitly so
529 // we can't deassert them. Leaving this in as a no-op since
530 // the prefetcher calls it to indicate that it no longer wants
531 // to request a prefetch, and someday that might be
532 // interesting again.
533 }
534
535 virtual unsigned int drain(Event *de);
536
537 virtual bool inCache(Addr addr) = 0;
538
539 virtual bool inMissQueue(Addr addr) = 0;
540
541 void incMissCount(PacketPtr pkt)
542 {
543 assert(pkt->req->masterId() < system->maxMasters());
544 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
545
546 if (missCount) {
547 --missCount;
548 if (missCount == 0)
549 exitSimLoop("A cache reached the maximum miss count");
550 }
551 }
552 void incHitCount(PacketPtr pkt)
553 {
554 assert(pkt->req->masterId() < system->maxMasters());
555 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
556
557 }
558
559};
560
561#endif //__BASE_CACHE_HH__
| 242 /** The number of targets for each MSHR. */
243 const int numTarget;
244
245 /** Do we forward snoops from mem side port through to cpu side port? */
246 bool forwardSnoops;
247
248 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
249 * never try to forward ownership and similar optimizations to the cpu
250 * side */
251 bool isTopLevel;
252
253 /**
254 * Bit vector of the blocking reasons for the access path.
255 * @sa #BlockedCause
256 */
257 uint8_t blocked;
258
259 /** Increasing order number assigned to each incoming request. */
260 uint64_t order;
261
262 /** Stores time the cache blocked for statistics. */
263 Tick blockedCycle;
264
265 /** Pointer to the MSHR that has no targets. */
266 MSHR *noTargetMSHR;
267
268 /** The number of misses to trigger an exit event. */
269 Counter missCount;
270
271 /** The drain event. */
272 Event *drainEvent;
273
274 /**
275 * The address range to which the cache responds on the CPU side.
276 * Normally this is all possible memory addresses. */
277 AddrRangeList addrRanges;
278
279 public:
280 /** System we are currently operating in. */
281 System *system;
282
283 // Statistics
284 /**
285 * @addtogroup CacheStatistics
286 * @{
287 */
288
289 /** Number of hits per thread for each type of command. @sa Packet::Command */
290 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
291 /** Number of hits for demand accesses. */
292 Stats::Formula demandHits;
293 /** Number of hit for all accesses. */
294 Stats::Formula overallHits;
295
296 /** Number of misses per thread for each type of command. @sa Packet::Command */
297 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
298 /** Number of misses for demand accesses. */
299 Stats::Formula demandMisses;
300 /** Number of misses for all accesses. */
301 Stats::Formula overallMisses;
302
303 /**
304 * Total number of cycles per thread/command spent waiting for a miss.
305 * Used to calculate the average miss latency.
306 */
307 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
308 /** Total number of cycles spent waiting for demand misses. */
309 Stats::Formula demandMissLatency;
310 /** Total number of cycles spent waiting for all misses. */
311 Stats::Formula overallMissLatency;
312
313 /** The number of accesses per command and thread. */
314 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
315 /** The number of demand accesses. */
316 Stats::Formula demandAccesses;
317 /** The number of overall accesses. */
318 Stats::Formula overallAccesses;
319
320 /** The miss rate per command and thread. */
321 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
322 /** The miss rate of all demand accesses. */
323 Stats::Formula demandMissRate;
324 /** The miss rate for all accesses. */
325 Stats::Formula overallMissRate;
326
327 /** The average miss latency per command and thread. */
328 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
329 /** The average miss latency for demand misses. */
330 Stats::Formula demandAvgMissLatency;
331 /** The average miss latency for all misses. */
332 Stats::Formula overallAvgMissLatency;
333
334 /** The total number of cycles blocked for each blocked cause. */
335 Stats::Vector blocked_cycles;
336 /** The number of times this cache blocked for each blocked cause. */
337 Stats::Vector blocked_causes;
338
339 /** The average number of cycles blocked for each blocked cause. */
340 Stats::Formula avg_blocked;
341
342 /** The number of fast writes (WH64) performed. */
343 Stats::Scalar fastWrites;
344
345 /** The number of cache copies performed. */
346 Stats::Scalar cacheCopies;
347
348 /** Number of blocks written back per thread. */
349 Stats::Vector writebacks;
350
351 /** Number of misses that hit in the MSHRs per command and thread. */
352 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
353 /** Demand misses that hit in the MSHRs. */
354 Stats::Formula demandMshrHits;
355 /** Total number of misses that hit in the MSHRs. */
356 Stats::Formula overallMshrHits;
357
358 /** Number of misses that miss in the MSHRs, per command and thread. */
359 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
360 /** Demand misses that miss in the MSHRs. */
361 Stats::Formula demandMshrMisses;
362 /** Total number of misses that miss in the MSHRs. */
363 Stats::Formula overallMshrMisses;
364
365 /** Number of misses that miss in the MSHRs, per command and thread. */
366 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
367 /** Total number of misses that miss in the MSHRs. */
368 Stats::Formula overallMshrUncacheable;
369
370 /** Total cycle latency of each MSHR miss, per command and thread. */
371 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
372 /** Total cycle latency of demand MSHR misses. */
373 Stats::Formula demandMshrMissLatency;
374 /** Total cycle latency of overall MSHR misses. */
375 Stats::Formula overallMshrMissLatency;
376
377 /** Total cycle latency of each MSHR miss, per command and thread. */
378 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
379 /** Total cycle latency of overall MSHR misses. */
380 Stats::Formula overallMshrUncacheableLatency;
381
382#if 0
383 /** The total number of MSHR accesses per command and thread. */
384 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
385 /** The total number of demand MSHR accesses. */
386 Stats::Formula demandMshrAccesses;
387 /** The total number of MSHR accesses. */
388 Stats::Formula overallMshrAccesses;
389#endif
390
391 /** The miss rate in the MSHRs pre command and thread. */
392 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
393 /** The demand miss rate in the MSHRs. */
394 Stats::Formula demandMshrMissRate;
395 /** The overall miss rate in the MSHRs. */
396 Stats::Formula overallMshrMissRate;
397
398 /** The average latency of an MSHR miss, per command and thread. */
399 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
400 /** The average latency of a demand MSHR miss. */
401 Stats::Formula demandAvgMshrMissLatency;
402 /** The average overall latency of an MSHR miss. */
403 Stats::Formula overallAvgMshrMissLatency;
404
405 /** The average latency of an MSHR miss, per command and thread. */
406 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
407 /** The average overall latency of an MSHR miss. */
408 Stats::Formula overallAvgMshrUncacheableLatency;
409
410 /** The number of times a thread hit its MSHR cap. */
411 Stats::Vector mshr_cap_events;
412 /** The number of times software prefetches caused the MSHR to block. */
413 Stats::Vector soft_prefetch_mshr_full;
414
415 Stats::Scalar mshr_no_allocate_misses;
416
417 /**
418 * @}
419 */
420
421 /**
422 * Register stats for this object.
423 */
424 virtual void regStats();
425
426 public:
427 typedef BaseCacheParams Params;
428 BaseCache(const Params *p);
429 ~BaseCache() {}
430
431 virtual void init();
432
433 virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
434 virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1);
435
436 /**
437 * Query block size of a cache.
438 * @return The block size
439 */
440 unsigned
441 getBlockSize() const
442 {
443 return blkSize;
444 }
445
446
447 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
448
449
450 const AddrRangeList &getAddrRanges() const { return addrRanges; }
451
452 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
453 {
454 assert(!pkt->req->isUncacheable());
455 return allocateBufferInternal(&mshrQueue,
456 blockAlign(pkt->getAddr()), blkSize,
457 pkt, time, requestBus);
458 }
459
460 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
461 {
462 assert(pkt->isWrite() && !pkt->isRead());
463 return allocateBufferInternal(&writeBuffer,
464 pkt->getAddr(), pkt->getSize(),
465 pkt, time, requestBus);
466 }
467
468 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
469 {
470 assert(pkt->req->isUncacheable());
471 assert(pkt->isRead());
472 return allocateBufferInternal(&mshrQueue,
473 pkt->getAddr(), pkt->getSize(),
474 pkt, time, requestBus);
475 }
476
477 /**
478 * Returns true if the cache is blocked for accesses.
479 */
480 bool isBlocked()
481 {
482 return blocked != 0;
483 }
484
485 /**
486 * Marks the access path of the cache as blocked for the given cause. This
487 * also sets the blocked flag in the slave interface.
488 * @param cause The reason for the cache blocking.
489 */
490 void setBlocked(BlockedCause cause)
491 {
492 uint8_t flag = 1 << cause;
493 if (blocked == 0) {
494 blocked_causes[cause]++;
495 blockedCycle = curTick();
496 cpuSidePort->setBlocked();
497 }
498 blocked |= flag;
499 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
500 }
501
502 /**
503 * Marks the cache as unblocked for the given cause. This also clears the
504 * blocked flags in the appropriate interfaces.
505 * @param cause The newly unblocked cause.
506 * @warning Calling this function can cause a blocked request on the bus to
507 * access the cache. The cache must be in a state to handle that request.
508 */
509 void clearBlocked(BlockedCause cause)
510 {
511 uint8_t flag = 1 << cause;
512 blocked &= ~flag;
513 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
514 if (blocked == 0) {
515 blocked_cycles[cause] += curTick() - blockedCycle;
516 cpuSidePort->clearBlocked();
517 }
518 }
519
520 /**
521 * Request the master bus for the given cause and time.
522 * @param cause The reason for the request.
523 * @param time The time to make the request.
524 */
525 void requestMemSideBus(RequestCause cause, Tick time)
526 {
527 memSidePort->requestBus(cause, time);
528 }
529
530 /**
531 * Clear the master bus request for the given cause.
532 * @param cause The request reason to clear.
533 */
534 void deassertMemSideBusRequest(RequestCause cause)
535 {
536 // Obsolete... we no longer signal bus requests explicitly so
537 // we can't deassert them. Leaving this in as a no-op since
538 // the prefetcher calls it to indicate that it no longer wants
539 // to request a prefetch, and someday that might be
540 // interesting again.
541 }
542
543 virtual unsigned int drain(Event *de);
544
545 virtual bool inCache(Addr addr) = 0;
546
547 virtual bool inMissQueue(Addr addr) = 0;
548
549 void incMissCount(PacketPtr pkt)
550 {
551 assert(pkt->req->masterId() < system->maxMasters());
552 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
553
554 if (missCount) {
555 --missCount;
556 if (missCount == 0)
557 exitSimLoop("A cache reached the maximum miss count");
558 }
559 }
560 void incHitCount(PacketPtr pkt)
561 {
562 assert(pkt->req->masterId() < system->maxMasters());
563 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
564
565 }
566
567};
568
569#endif //__BASE_CACHE_HH__
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