1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
135 }
136
137 /**
138 * Schedule the transmissions of a response packet at a given
139 * point in time.
140 *
141 * @param pkt response packet
142 * @param when time to send the response
143 */
144 void respond(PacketPtr pkt, Tick time) {
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
135 }
136
137 /**
138 * Schedule the transmissions of a response packet at a given
139 * point in time.
140 *
141 * @param pkt response packet
142 * @param when time to send the response
143 */
144 void respond(PacketPtr pkt, Tick time) {
|
146 }
147
148 protected:
149
150 CacheMasterPort(const std::string &_name, BaseCache *_cache,
151 PacketQueue &_queue) :
152 QueuedMasterPort(_name, _cache, _queue)
153 { }
154
155 /**
156 * Memory-side port always snoops.
157 *
158 * @return always true
159 */
160 virtual bool isSnooping() const { return true; }
161 };
162
163 /**
164 * A cache slave port is used for the CPU-side port of the cache,
165 * and it is basically a simple timing port that uses a transmit
166 * list for responses to the CPU (or connected master). In
167 * addition, it has the functionality to block the port for
168 * incoming requests. If blocked, the port will issue a retry once
169 * unblocked.
170 */
171 class CacheSlavePort : public QueuedSlavePort
172 {
173
174 public:
175
176 /** Do not accept any new requests. */
177 void setBlocked();
178
179 /** Return to normal operation and accept new requests. */
180 void clearBlocked();
181
182 /**
183 * Schedule the transmissions of a response packet at a given
184 * point in time.
185 *
186 * @param pkt response packet
187 * @param when time to send the response
188 */
189 void respond(PacketPtr pkt, Tick time) {
190 queue.schedSendTiming(pkt, time);
191 }
192
193 protected:
194
195 CacheSlavePort(const std::string &_name, BaseCache *_cache,
196 const std::string &_label);
197
198 /** A normal packet queue used to store responses. */
199 PacketQueue queue;
200
201 bool blocked;
202
203 bool mustSendRetry;
204
205 private:
206
207 EventWrapper<Port, &Port::sendRetry> sendRetryEvent;
208
209 };
210
211 CacheSlavePort *cpuSidePort;
212 CacheMasterPort *memSidePort;
213
214 protected:
215
216 /** Miss status registers */
217 MSHRQueue mshrQueue;
218
219 /** Write/writeback buffer */
220 MSHRQueue writeBuffer;
221
222 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
223 PacketPtr pkt, Tick time, bool requestBus)
224 {
225 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
226
227 if (mq->isFull()) {
228 setBlocked((BlockedCause)mq->index);
229 }
230
231 if (requestBus) {
232 requestMemSideBus((RequestCause)mq->index, time);
233 }
234
235 return mshr;
236 }
237
238 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
239 {
240 MSHRQueue *mq = mshr->queue;
241 bool wasFull = mq->isFull();
242 mq->markInService(mshr, pkt);
243 if (wasFull && !mq->isFull()) {
244 clearBlocked((BlockedCause)mq->index);
245 }
246 }
247
248 /** Block size of this cache */
249 const unsigned blkSize;
250
251 /**
252 * The latency of a hit in this device.
253 */
254 int hitLatency;
255
256 /** The number of targets for each MSHR. */
257 const int numTarget;
258
259 /** Do we forward snoops from mem side port through to cpu side port? */
260 bool forwardSnoops;
261
262 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
263 * never try to forward ownership and similar optimizations to the cpu
264 * side */
265 bool isTopLevel;
266
267 /**
268 * Bit vector of the blocking reasons for the access path.
269 * @sa #BlockedCause
270 */
271 uint8_t blocked;
272
273 /** Increasing order number assigned to each incoming request. */
274 uint64_t order;
275
276 /** Stores time the cache blocked for statistics. */
277 Tick blockedCycle;
278
279 /** Pointer to the MSHR that has no targets. */
280 MSHR *noTargetMSHR;
281
282 /** The number of misses to trigger an exit event. */
283 Counter missCount;
284
285 /** The drain event. */
286 Event *drainEvent;
287
288 /**
289 * The address range to which the cache responds on the CPU side.
290 * Normally this is all possible memory addresses. */
291 AddrRangeList addrRanges;
292
293 public:
294 /** System we are currently operating in. */
295 System *system;
296
297 // Statistics
298 /**
299 * @addtogroup CacheStatistics
300 * @{
301 */
302
303 /** Number of hits per thread for each type of command. @sa Packet::Command */
304 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
305 /** Number of hits for demand accesses. */
306 Stats::Formula demandHits;
307 /** Number of hit for all accesses. */
308 Stats::Formula overallHits;
309
310 /** Number of misses per thread for each type of command. @sa Packet::Command */
311 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
312 /** Number of misses for demand accesses. */
313 Stats::Formula demandMisses;
314 /** Number of misses for all accesses. */
315 Stats::Formula overallMisses;
316
317 /**
318 * Total number of cycles per thread/command spent waiting for a miss.
319 * Used to calculate the average miss latency.
320 */
321 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
322 /** Total number of cycles spent waiting for demand misses. */
323 Stats::Formula demandMissLatency;
324 /** Total number of cycles spent waiting for all misses. */
325 Stats::Formula overallMissLatency;
326
327 /** The number of accesses per command and thread. */
328 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
329 /** The number of demand accesses. */
330 Stats::Formula demandAccesses;
331 /** The number of overall accesses. */
332 Stats::Formula overallAccesses;
333
334 /** The miss rate per command and thread. */
335 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
336 /** The miss rate of all demand accesses. */
337 Stats::Formula demandMissRate;
338 /** The miss rate for all accesses. */
339 Stats::Formula overallMissRate;
340
341 /** The average miss latency per command and thread. */
342 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
343 /** The average miss latency for demand misses. */
344 Stats::Formula demandAvgMissLatency;
345 /** The average miss latency for all misses. */
346 Stats::Formula overallAvgMissLatency;
347
348 /** The total number of cycles blocked for each blocked cause. */
349 Stats::Vector blocked_cycles;
350 /** The number of times this cache blocked for each blocked cause. */
351 Stats::Vector blocked_causes;
352
353 /** The average number of cycles blocked for each blocked cause. */
354 Stats::Formula avg_blocked;
355
356 /** The number of fast writes (WH64) performed. */
357 Stats::Scalar fastWrites;
358
359 /** The number of cache copies performed. */
360 Stats::Scalar cacheCopies;
361
362 /** Number of blocks written back per thread. */
363 Stats::Vector writebacks;
364
365 /** Number of misses that hit in the MSHRs per command and thread. */
366 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
367 /** Demand misses that hit in the MSHRs. */
368 Stats::Formula demandMshrHits;
369 /** Total number of misses that hit in the MSHRs. */
370 Stats::Formula overallMshrHits;
371
372 /** Number of misses that miss in the MSHRs, per command and thread. */
373 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
374 /** Demand misses that miss in the MSHRs. */
375 Stats::Formula demandMshrMisses;
376 /** Total number of misses that miss in the MSHRs. */
377 Stats::Formula overallMshrMisses;
378
379 /** Number of misses that miss in the MSHRs, per command and thread. */
380 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
381 /** Total number of misses that miss in the MSHRs. */
382 Stats::Formula overallMshrUncacheable;
383
384 /** Total cycle latency of each MSHR miss, per command and thread. */
385 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
386 /** Total cycle latency of demand MSHR misses. */
387 Stats::Formula demandMshrMissLatency;
388 /** Total cycle latency of overall MSHR misses. */
389 Stats::Formula overallMshrMissLatency;
390
391 /** Total cycle latency of each MSHR miss, per command and thread. */
392 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
393 /** Total cycle latency of overall MSHR misses. */
394 Stats::Formula overallMshrUncacheableLatency;
395
396#if 0
397 /** The total number of MSHR accesses per command and thread. */
398 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
399 /** The total number of demand MSHR accesses. */
400 Stats::Formula demandMshrAccesses;
401 /** The total number of MSHR accesses. */
402 Stats::Formula overallMshrAccesses;
403#endif
404
405 /** The miss rate in the MSHRs pre command and thread. */
406 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
407 /** The demand miss rate in the MSHRs. */
408 Stats::Formula demandMshrMissRate;
409 /** The overall miss rate in the MSHRs. */
410 Stats::Formula overallMshrMissRate;
411
412 /** The average latency of an MSHR miss, per command and thread. */
413 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
414 /** The average latency of a demand MSHR miss. */
415 Stats::Formula demandAvgMshrMissLatency;
416 /** The average overall latency of an MSHR miss. */
417 Stats::Formula overallAvgMshrMissLatency;
418
419 /** The average latency of an MSHR miss, per command and thread. */
420 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
421 /** The average overall latency of an MSHR miss. */
422 Stats::Formula overallAvgMshrUncacheableLatency;
423
424 /** The number of times a thread hit its MSHR cap. */
425 Stats::Vector mshr_cap_events;
426 /** The number of times software prefetches caused the MSHR to block. */
427 Stats::Vector soft_prefetch_mshr_full;
428
429 Stats::Scalar mshr_no_allocate_misses;
430
431 /**
432 * @}
433 */
434
435 /**
436 * Register stats for this object.
437 */
438 virtual void regStats();
439
440 public:
441 typedef BaseCacheParams Params;
442 BaseCache(const Params *p);
443 ~BaseCache() {}
444
445 virtual void init();
446
447 virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
448 virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1);
449
450 /**
451 * Query block size of a cache.
452 * @return The block size
453 */
454 unsigned
455 getBlockSize() const
456 {
457 return blkSize;
458 }
459
460
461 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
462
463
464 const AddrRangeList &getAddrRanges() const { return addrRanges; }
465
466 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
467 {
468 assert(!pkt->req->isUncacheable());
469 return allocateBufferInternal(&mshrQueue,
470 blockAlign(pkt->getAddr()), blkSize,
471 pkt, time, requestBus);
472 }
473
474 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
475 {
476 assert(pkt->isWrite() && !pkt->isRead());
477 return allocateBufferInternal(&writeBuffer,
478 pkt->getAddr(), pkt->getSize(),
479 pkt, time, requestBus);
480 }
481
482 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
483 {
484 assert(pkt->req->isUncacheable());
485 assert(pkt->isRead());
486 return allocateBufferInternal(&mshrQueue,
487 pkt->getAddr(), pkt->getSize(),
488 pkt, time, requestBus);
489 }
490
491 /**
492 * Returns true if the cache is blocked for accesses.
493 */
494 bool isBlocked()
495 {
496 return blocked != 0;
497 }
498
499 /**
500 * Marks the access path of the cache as blocked for the given cause. This
501 * also sets the blocked flag in the slave interface.
502 * @param cause The reason for the cache blocking.
503 */
504 void setBlocked(BlockedCause cause)
505 {
506 uint8_t flag = 1 << cause;
507 if (blocked == 0) {
508 blocked_causes[cause]++;
509 blockedCycle = curTick();
510 cpuSidePort->setBlocked();
511 }
512 blocked |= flag;
513 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
514 }
515
516 /**
517 * Marks the cache as unblocked for the given cause. This also clears the
518 * blocked flags in the appropriate interfaces.
519 * @param cause The newly unblocked cause.
520 * @warning Calling this function can cause a blocked request on the bus to
521 * access the cache. The cache must be in a state to handle that request.
522 */
523 void clearBlocked(BlockedCause cause)
524 {
525 uint8_t flag = 1 << cause;
526 blocked &= ~flag;
527 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
528 if (blocked == 0) {
529 blocked_cycles[cause] += curTick() - blockedCycle;
530 cpuSidePort->clearBlocked();
531 }
532 }
533
534 /**
535 * Request the master bus for the given cause and time.
536 * @param cause The reason for the request.
537 * @param time The time to make the request.
538 */
539 void requestMemSideBus(RequestCause cause, Tick time)
540 {
541 memSidePort->requestBus(cause, time);
542 }
543
544 /**
545 * Clear the master bus request for the given cause.
546 * @param cause The request reason to clear.
547 */
548 void deassertMemSideBusRequest(RequestCause cause)
549 {
550 // Obsolete... we no longer signal bus requests explicitly so
551 // we can't deassert them. Leaving this in as a no-op since
552 // the prefetcher calls it to indicate that it no longer wants
553 // to request a prefetch, and someday that might be
554 // interesting again.
555 }
556
557 virtual unsigned int drain(Event *de);
558
559 virtual bool inCache(Addr addr) = 0;
560
561 virtual bool inMissQueue(Addr addr) = 0;
562
563 void incMissCount(PacketPtr pkt)
564 {
565 assert(pkt->req->masterId() < system->maxMasters());
566 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
567
568 if (missCount) {
569 --missCount;
570 if (missCount == 0)
571 exitSimLoop("A cache reached the maximum miss count");
572 }
573 }
574 void incHitCount(PacketPtr pkt)
575 {
576 assert(pkt->req->masterId() < system->maxMasters());
577 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
578
579 }
580
581};
582
583#endif //__BASE_CACHE_HH__
| 146 }
147
148 protected:
149
150 CacheMasterPort(const std::string &_name, BaseCache *_cache,
151 PacketQueue &_queue) :
152 QueuedMasterPort(_name, _cache, _queue)
153 { }
154
155 /**
156 * Memory-side port always snoops.
157 *
158 * @return always true
159 */
160 virtual bool isSnooping() const { return true; }
161 };
162
163 /**
164 * A cache slave port is used for the CPU-side port of the cache,
165 * and it is basically a simple timing port that uses a transmit
166 * list for responses to the CPU (or connected master). In
167 * addition, it has the functionality to block the port for
168 * incoming requests. If blocked, the port will issue a retry once
169 * unblocked.
170 */
171 class CacheSlavePort : public QueuedSlavePort
172 {
173
174 public:
175
176 /** Do not accept any new requests. */
177 void setBlocked();
178
179 /** Return to normal operation and accept new requests. */
180 void clearBlocked();
181
182 /**
183 * Schedule the transmissions of a response packet at a given
184 * point in time.
185 *
186 * @param pkt response packet
187 * @param when time to send the response
188 */
189 void respond(PacketPtr pkt, Tick time) {
190 queue.schedSendTiming(pkt, time);
191 }
192
193 protected:
194
195 CacheSlavePort(const std::string &_name, BaseCache *_cache,
196 const std::string &_label);
197
198 /** A normal packet queue used to store responses. */
199 PacketQueue queue;
200
201 bool blocked;
202
203 bool mustSendRetry;
204
205 private:
206
207 EventWrapper<Port, &Port::sendRetry> sendRetryEvent;
208
209 };
210
211 CacheSlavePort *cpuSidePort;
212 CacheMasterPort *memSidePort;
213
214 protected:
215
216 /** Miss status registers */
217 MSHRQueue mshrQueue;
218
219 /** Write/writeback buffer */
220 MSHRQueue writeBuffer;
221
222 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
223 PacketPtr pkt, Tick time, bool requestBus)
224 {
225 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
226
227 if (mq->isFull()) {
228 setBlocked((BlockedCause)mq->index);
229 }
230
231 if (requestBus) {
232 requestMemSideBus((RequestCause)mq->index, time);
233 }
234
235 return mshr;
236 }
237
238 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
239 {
240 MSHRQueue *mq = mshr->queue;
241 bool wasFull = mq->isFull();
242 mq->markInService(mshr, pkt);
243 if (wasFull && !mq->isFull()) {
244 clearBlocked((BlockedCause)mq->index);
245 }
246 }
247
248 /** Block size of this cache */
249 const unsigned blkSize;
250
251 /**
252 * The latency of a hit in this device.
253 */
254 int hitLatency;
255
256 /** The number of targets for each MSHR. */
257 const int numTarget;
258
259 /** Do we forward snoops from mem side port through to cpu side port? */
260 bool forwardSnoops;
261
262 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
263 * never try to forward ownership and similar optimizations to the cpu
264 * side */
265 bool isTopLevel;
266
267 /**
268 * Bit vector of the blocking reasons for the access path.
269 * @sa #BlockedCause
270 */
271 uint8_t blocked;
272
273 /** Increasing order number assigned to each incoming request. */
274 uint64_t order;
275
276 /** Stores time the cache blocked for statistics. */
277 Tick blockedCycle;
278
279 /** Pointer to the MSHR that has no targets. */
280 MSHR *noTargetMSHR;
281
282 /** The number of misses to trigger an exit event. */
283 Counter missCount;
284
285 /** The drain event. */
286 Event *drainEvent;
287
288 /**
289 * The address range to which the cache responds on the CPU side.
290 * Normally this is all possible memory addresses. */
291 AddrRangeList addrRanges;
292
293 public:
294 /** System we are currently operating in. */
295 System *system;
296
297 // Statistics
298 /**
299 * @addtogroup CacheStatistics
300 * @{
301 */
302
303 /** Number of hits per thread for each type of command. @sa Packet::Command */
304 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
305 /** Number of hits for demand accesses. */
306 Stats::Formula demandHits;
307 /** Number of hit for all accesses. */
308 Stats::Formula overallHits;
309
310 /** Number of misses per thread for each type of command. @sa Packet::Command */
311 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
312 /** Number of misses for demand accesses. */
313 Stats::Formula demandMisses;
314 /** Number of misses for all accesses. */
315 Stats::Formula overallMisses;
316
317 /**
318 * Total number of cycles per thread/command spent waiting for a miss.
319 * Used to calculate the average miss latency.
320 */
321 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
322 /** Total number of cycles spent waiting for demand misses. */
323 Stats::Formula demandMissLatency;
324 /** Total number of cycles spent waiting for all misses. */
325 Stats::Formula overallMissLatency;
326
327 /** The number of accesses per command and thread. */
328 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
329 /** The number of demand accesses. */
330 Stats::Formula demandAccesses;
331 /** The number of overall accesses. */
332 Stats::Formula overallAccesses;
333
334 /** The miss rate per command and thread. */
335 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
336 /** The miss rate of all demand accesses. */
337 Stats::Formula demandMissRate;
338 /** The miss rate for all accesses. */
339 Stats::Formula overallMissRate;
340
341 /** The average miss latency per command and thread. */
342 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
343 /** The average miss latency for demand misses. */
344 Stats::Formula demandAvgMissLatency;
345 /** The average miss latency for all misses. */
346 Stats::Formula overallAvgMissLatency;
347
348 /** The total number of cycles blocked for each blocked cause. */
349 Stats::Vector blocked_cycles;
350 /** The number of times this cache blocked for each blocked cause. */
351 Stats::Vector blocked_causes;
352
353 /** The average number of cycles blocked for each blocked cause. */
354 Stats::Formula avg_blocked;
355
356 /** The number of fast writes (WH64) performed. */
357 Stats::Scalar fastWrites;
358
359 /** The number of cache copies performed. */
360 Stats::Scalar cacheCopies;
361
362 /** Number of blocks written back per thread. */
363 Stats::Vector writebacks;
364
365 /** Number of misses that hit in the MSHRs per command and thread. */
366 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
367 /** Demand misses that hit in the MSHRs. */
368 Stats::Formula demandMshrHits;
369 /** Total number of misses that hit in the MSHRs. */
370 Stats::Formula overallMshrHits;
371
372 /** Number of misses that miss in the MSHRs, per command and thread. */
373 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
374 /** Demand misses that miss in the MSHRs. */
375 Stats::Formula demandMshrMisses;
376 /** Total number of misses that miss in the MSHRs. */
377 Stats::Formula overallMshrMisses;
378
379 /** Number of misses that miss in the MSHRs, per command and thread. */
380 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
381 /** Total number of misses that miss in the MSHRs. */
382 Stats::Formula overallMshrUncacheable;
383
384 /** Total cycle latency of each MSHR miss, per command and thread. */
385 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
386 /** Total cycle latency of demand MSHR misses. */
387 Stats::Formula demandMshrMissLatency;
388 /** Total cycle latency of overall MSHR misses. */
389 Stats::Formula overallMshrMissLatency;
390
391 /** Total cycle latency of each MSHR miss, per command and thread. */
392 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
393 /** Total cycle latency of overall MSHR misses. */
394 Stats::Formula overallMshrUncacheableLatency;
395
396#if 0
397 /** The total number of MSHR accesses per command and thread. */
398 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
399 /** The total number of demand MSHR accesses. */
400 Stats::Formula demandMshrAccesses;
401 /** The total number of MSHR accesses. */
402 Stats::Formula overallMshrAccesses;
403#endif
404
405 /** The miss rate in the MSHRs pre command and thread. */
406 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
407 /** The demand miss rate in the MSHRs. */
408 Stats::Formula demandMshrMissRate;
409 /** The overall miss rate in the MSHRs. */
410 Stats::Formula overallMshrMissRate;
411
412 /** The average latency of an MSHR miss, per command and thread. */
413 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
414 /** The average latency of a demand MSHR miss. */
415 Stats::Formula demandAvgMshrMissLatency;
416 /** The average overall latency of an MSHR miss. */
417 Stats::Formula overallAvgMshrMissLatency;
418
419 /** The average latency of an MSHR miss, per command and thread. */
420 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
421 /** The average overall latency of an MSHR miss. */
422 Stats::Formula overallAvgMshrUncacheableLatency;
423
424 /** The number of times a thread hit its MSHR cap. */
425 Stats::Vector mshr_cap_events;
426 /** The number of times software prefetches caused the MSHR to block. */
427 Stats::Vector soft_prefetch_mshr_full;
428
429 Stats::Scalar mshr_no_allocate_misses;
430
431 /**
432 * @}
433 */
434
435 /**
436 * Register stats for this object.
437 */
438 virtual void regStats();
439
440 public:
441 typedef BaseCacheParams Params;
442 BaseCache(const Params *p);
443 ~BaseCache() {}
444
445 virtual void init();
446
447 virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1);
448 virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1);
449
450 /**
451 * Query block size of a cache.
452 * @return The block size
453 */
454 unsigned
455 getBlockSize() const
456 {
457 return blkSize;
458 }
459
460
461 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
462
463
464 const AddrRangeList &getAddrRanges() const { return addrRanges; }
465
466 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
467 {
468 assert(!pkt->req->isUncacheable());
469 return allocateBufferInternal(&mshrQueue,
470 blockAlign(pkt->getAddr()), blkSize,
471 pkt, time, requestBus);
472 }
473
474 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
475 {
476 assert(pkt->isWrite() && !pkt->isRead());
477 return allocateBufferInternal(&writeBuffer,
478 pkt->getAddr(), pkt->getSize(),
479 pkt, time, requestBus);
480 }
481
482 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
483 {
484 assert(pkt->req->isUncacheable());
485 assert(pkt->isRead());
486 return allocateBufferInternal(&mshrQueue,
487 pkt->getAddr(), pkt->getSize(),
488 pkt, time, requestBus);
489 }
490
491 /**
492 * Returns true if the cache is blocked for accesses.
493 */
494 bool isBlocked()
495 {
496 return blocked != 0;
497 }
498
499 /**
500 * Marks the access path of the cache as blocked for the given cause. This
501 * also sets the blocked flag in the slave interface.
502 * @param cause The reason for the cache blocking.
503 */
504 void setBlocked(BlockedCause cause)
505 {
506 uint8_t flag = 1 << cause;
507 if (blocked == 0) {
508 blocked_causes[cause]++;
509 blockedCycle = curTick();
510 cpuSidePort->setBlocked();
511 }
512 blocked |= flag;
513 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
514 }
515
516 /**
517 * Marks the cache as unblocked for the given cause. This also clears the
518 * blocked flags in the appropriate interfaces.
519 * @param cause The newly unblocked cause.
520 * @warning Calling this function can cause a blocked request on the bus to
521 * access the cache. The cache must be in a state to handle that request.
522 */
523 void clearBlocked(BlockedCause cause)
524 {
525 uint8_t flag = 1 << cause;
526 blocked &= ~flag;
527 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
528 if (blocked == 0) {
529 blocked_cycles[cause] += curTick() - blockedCycle;
530 cpuSidePort->clearBlocked();
531 }
532 }
533
534 /**
535 * Request the master bus for the given cause and time.
536 * @param cause The reason for the request.
537 * @param time The time to make the request.
538 */
539 void requestMemSideBus(RequestCause cause, Tick time)
540 {
541 memSidePort->requestBus(cause, time);
542 }
543
544 /**
545 * Clear the master bus request for the given cause.
546 * @param cause The request reason to clear.
547 */
548 void deassertMemSideBusRequest(RequestCause cause)
549 {
550 // Obsolete... we no longer signal bus requests explicitly so
551 // we can't deassert them. Leaving this in as a no-op since
552 // the prefetcher calls it to indicate that it no longer wants
553 // to request a prefetch, and someday that might be
554 // interesting again.
555 }
556
557 virtual unsigned int drain(Event *de);
558
559 virtual bool inCache(Addr addr) = 0;
560
561 virtual bool inMissQueue(Addr addr) = 0;
562
563 void incMissCount(PacketPtr pkt)
564 {
565 assert(pkt->req->masterId() < system->maxMasters());
566 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
567
568 if (missCount) {
569 --missCount;
570 if (missCount == 0)
571 exitSimLoop("A cache reached the maximum miss count");
572 }
573 }
574 void incHitCount(PacketPtr pkt)
575 {
576 assert(pkt->req->masterId() < system->maxMasters());
577 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
578
579 }
580
581};
582
583#endif //__BASE_CACHE_HH__
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