1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Steve Reinhardt
30 * Ron Dreslinski
31 */
32
33/**
34 * @file
35 * Declares a basic cache interface BaseCache.
36 */
37
38#ifndef __BASE_CACHE_HH__
39#define __BASE_CACHE_HH__
40
41#include <vector>
42#include <string>
43#include <list>
44#include <algorithm>
45
46#include "base/misc.hh"
47#include "base/statistics.hh"
48#include "base/trace.hh"
49#include "base/types.hh"
| 1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Erik Hallnor
29 * Steve Reinhardt
30 * Ron Dreslinski
31 */
32
33/**
34 * @file
35 * Declares a basic cache interface BaseCache.
36 */
37
38#ifndef __BASE_CACHE_HH__
39#define __BASE_CACHE_HH__
40
41#include <vector>
42#include <string>
43#include <list>
44#include <algorithm>
45
46#include "base/misc.hh"
47#include "base/statistics.hh"
48#include "base/trace.hh"
49#include "base/types.hh"
|
| 50#include "config/full_system.hh"
|
50#include "mem/cache/mshr_queue.hh"
51#include "mem/mem_object.hh"
52#include "mem/packet.hh"
53#include "mem/tport.hh"
54#include "mem/request.hh"
55#include "params/BaseCache.hh"
56#include "sim/eventq.hh"
57#include "sim/sim_exit.hh"
58
59class MSHR;
60/**
61 * A basic cache interface. Implements some common functions for speed.
62 */
63class BaseCache : public MemObject
64{
65 /**
66 * Indexes to enumerate the MSHR queues.
67 */
68 enum MSHRQueueIndex {
69 MSHRQueue_MSHRs,
70 MSHRQueue_WriteBuffer
71 };
72
73 /**
74 * Reasons for caches to be blocked.
75 */
76 enum BlockedCause {
77 Blocked_NoMSHRs = MSHRQueue_MSHRs,
78 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
79 Blocked_NoTargets,
80 NUM_BLOCKED_CAUSES
81 };
82
83 public:
84 /**
85 * Reasons for cache to request a bus.
86 */
87 enum RequestCause {
88 Request_MSHR = MSHRQueue_MSHRs,
89 Request_WB = MSHRQueue_WriteBuffer,
90 Request_PF,
91 NUM_REQUEST_CAUSES
92 };
93
94 private:
95
96 class CachePort : public SimpleTimingPort
97 {
98 public:
99 BaseCache *cache;
100
101 protected:
102 CachePort(const std::string &_name, BaseCache *_cache,
103 const std::string &_label);
104
105 virtual void recvStatusChange(Status status);
106
107 virtual unsigned deviceBlockSize() const;
108
109 bool recvRetryCommon();
110
111 typedef EventWrapper<Port, &Port::sendRetry>
112 SendRetryEvent;
113
114 const std::string label;
115
116 public:
117 void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; }
118
119 void setBlocked();
120
121 void clearBlocked();
122
123 bool checkFunctional(PacketPtr pkt);
124
125 CachePort *otherPort;
126
127 bool blocked;
128
129 bool mustSendRetry;
130
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 if (!waitingOnRetry) {
135 schedSendEvent(time);
136 }
137 }
138
139 void respond(PacketPtr pkt, Tick time) {
140 schedSendTiming(pkt, time);
141 }
142 };
143
144 public: //Made public so coherence can get at it.
145 CachePort *cpuSidePort;
146 CachePort *memSidePort;
147
148 protected:
149
150 /** Miss status registers */
151 MSHRQueue mshrQueue;
152
153 /** Write/writeback buffer */
154 MSHRQueue writeBuffer;
155
156 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
157 PacketPtr pkt, Tick time, bool requestBus)
158 {
159 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
160
161 if (mq->isFull()) {
162 setBlocked((BlockedCause)mq->index);
163 }
164
165 if (requestBus) {
166 requestMemSideBus((RequestCause)mq->index, time);
167 }
168
169 return mshr;
170 }
171
172 void markInServiceInternal(MSHR *mshr)
173 {
174 MSHRQueue *mq = mshr->queue;
175 bool wasFull = mq->isFull();
176 mq->markInService(mshr);
177 if (wasFull && !mq->isFull()) {
178 clearBlocked((BlockedCause)mq->index);
179 }
180 }
181
182 /** Block size of this cache */
183 const unsigned blkSize;
184
185 /**
186 * The latency of a hit in this device.
187 */
188 int hitLatency;
189
190 /** The number of targets for each MSHR. */
191 const int numTarget;
192
193 /** Do we forward snoops from mem side port through to cpu side port? */
194 bool forwardSnoops;
195
196 /**
197 * Bit vector of the blocking reasons for the access path.
198 * @sa #BlockedCause
199 */
200 uint8_t blocked;
201
202 /** Increasing order number assigned to each incoming request. */
203 uint64_t order;
204
205 /** Stores time the cache blocked for statistics. */
206 Tick blockedCycle;
207
208 /** Pointer to the MSHR that has no targets. */
209 MSHR *noTargetMSHR;
210
211 /** The number of misses to trigger an exit event. */
212 Counter missCount;
213
214 /** The drain event. */
215 Event *drainEvent;
216
217 /**
218 * The address range to which the cache responds on the CPU side.
219 * Normally this is all possible memory addresses. */
220 Range<Addr> addrRange;
221
| 51#include "mem/cache/mshr_queue.hh"
52#include "mem/mem_object.hh"
53#include "mem/packet.hh"
54#include "mem/tport.hh"
55#include "mem/request.hh"
56#include "params/BaseCache.hh"
57#include "sim/eventq.hh"
58#include "sim/sim_exit.hh"
59
60class MSHR;
61/**
62 * A basic cache interface. Implements some common functions for speed.
63 */
64class BaseCache : public MemObject
65{
66 /**
67 * Indexes to enumerate the MSHR queues.
68 */
69 enum MSHRQueueIndex {
70 MSHRQueue_MSHRs,
71 MSHRQueue_WriteBuffer
72 };
73
74 /**
75 * Reasons for caches to be blocked.
76 */
77 enum BlockedCause {
78 Blocked_NoMSHRs = MSHRQueue_MSHRs,
79 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
80 Blocked_NoTargets,
81 NUM_BLOCKED_CAUSES
82 };
83
84 public:
85 /**
86 * Reasons for cache to request a bus.
87 */
88 enum RequestCause {
89 Request_MSHR = MSHRQueue_MSHRs,
90 Request_WB = MSHRQueue_WriteBuffer,
91 Request_PF,
92 NUM_REQUEST_CAUSES
93 };
94
95 private:
96
97 class CachePort : public SimpleTimingPort
98 {
99 public:
100 BaseCache *cache;
101
102 protected:
103 CachePort(const std::string &_name, BaseCache *_cache,
104 const std::string &_label);
105
106 virtual void recvStatusChange(Status status);
107
108 virtual unsigned deviceBlockSize() const;
109
110 bool recvRetryCommon();
111
112 typedef EventWrapper<Port, &Port::sendRetry>
113 SendRetryEvent;
114
115 const std::string label;
116
117 public:
118 void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; }
119
120 void setBlocked();
121
122 void clearBlocked();
123
124 bool checkFunctional(PacketPtr pkt);
125
126 CachePort *otherPort;
127
128 bool blocked;
129
130 bool mustSendRetry;
131
132 void requestBus(RequestCause cause, Tick time)
133 {
134 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
135 if (!waitingOnRetry) {
136 schedSendEvent(time);
137 }
138 }
139
140 void respond(PacketPtr pkt, Tick time) {
141 schedSendTiming(pkt, time);
142 }
143 };
144
145 public: //Made public so coherence can get at it.
146 CachePort *cpuSidePort;
147 CachePort *memSidePort;
148
149 protected:
150
151 /** Miss status registers */
152 MSHRQueue mshrQueue;
153
154 /** Write/writeback buffer */
155 MSHRQueue writeBuffer;
156
157 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
158 PacketPtr pkt, Tick time, bool requestBus)
159 {
160 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
161
162 if (mq->isFull()) {
163 setBlocked((BlockedCause)mq->index);
164 }
165
166 if (requestBus) {
167 requestMemSideBus((RequestCause)mq->index, time);
168 }
169
170 return mshr;
171 }
172
173 void markInServiceInternal(MSHR *mshr)
174 {
175 MSHRQueue *mq = mshr->queue;
176 bool wasFull = mq->isFull();
177 mq->markInService(mshr);
178 if (wasFull && !mq->isFull()) {
179 clearBlocked((BlockedCause)mq->index);
180 }
181 }
182
183 /** Block size of this cache */
184 const unsigned blkSize;
185
186 /**
187 * The latency of a hit in this device.
188 */
189 int hitLatency;
190
191 /** The number of targets for each MSHR. */
192 const int numTarget;
193
194 /** Do we forward snoops from mem side port through to cpu side port? */
195 bool forwardSnoops;
196
197 /**
198 * Bit vector of the blocking reasons for the access path.
199 * @sa #BlockedCause
200 */
201 uint8_t blocked;
202
203 /** Increasing order number assigned to each incoming request. */
204 uint64_t order;
205
206 /** Stores time the cache blocked for statistics. */
207 Tick blockedCycle;
208
209 /** Pointer to the MSHR that has no targets. */
210 MSHR *noTargetMSHR;
211
212 /** The number of misses to trigger an exit event. */
213 Counter missCount;
214
215 /** The drain event. */
216 Event *drainEvent;
217
218 /**
219 * The address range to which the cache responds on the CPU side.
220 * Normally this is all possible memory addresses. */
221 Range<Addr> addrRange;
222
|
| 223 /** number of cpus sharing this cache - from config file */
224 int _numCpus;
225
|
222 public:
| 226 public:
|
| 227 int numCpus() { return _numCpus; }
|
223 // Statistics
224 /**
225 * @addtogroup CacheStatistics
226 * @{
227 */
228
229 /** Number of hits per thread for each type of command. @sa Packet::Command */
230 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
231 /** Number of hits for demand accesses. */
232 Stats::Formula demandHits;
233 /** Number of hit for all accesses. */
234 Stats::Formula overallHits;
235
236 /** Number of misses per thread for each type of command. @sa Packet::Command */
237 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
238 /** Number of misses for demand accesses. */
239 Stats::Formula demandMisses;
240 /** Number of misses for all accesses. */
241 Stats::Formula overallMisses;
242
243 /**
244 * Total number of cycles per thread/command spent waiting for a miss.
245 * Used to calculate the average miss latency.
246 */
247 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
248 /** Total number of cycles spent waiting for demand misses. */
249 Stats::Formula demandMissLatency;
250 /** Total number of cycles spent waiting for all misses. */
251 Stats::Formula overallMissLatency;
252
253 /** The number of accesses per command and thread. */
254 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
255 /** The number of demand accesses. */
256 Stats::Formula demandAccesses;
257 /** The number of overall accesses. */
258 Stats::Formula overallAccesses;
259
260 /** The miss rate per command and thread. */
261 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
262 /** The miss rate of all demand accesses. */
263 Stats::Formula demandMissRate;
264 /** The miss rate for all accesses. */
265 Stats::Formula overallMissRate;
266
267 /** The average miss latency per command and thread. */
268 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
269 /** The average miss latency for demand misses. */
270 Stats::Formula demandAvgMissLatency;
271 /** The average miss latency for all misses. */
272 Stats::Formula overallAvgMissLatency;
273
274 /** The total number of cycles blocked for each blocked cause. */
275 Stats::Vector blocked_cycles;
276 /** The number of times this cache blocked for each blocked cause. */
277 Stats::Vector blocked_causes;
278
279 /** The average number of cycles blocked for each blocked cause. */
280 Stats::Formula avg_blocked;
281
282 /** The number of fast writes (WH64) performed. */
283 Stats::Scalar fastWrites;
284
285 /** The number of cache copies performed. */
286 Stats::Scalar cacheCopies;
287
288 /** Number of blocks written back per thread. */
289 Stats::Vector writebacks;
290
291 /** Number of misses that hit in the MSHRs per command and thread. */
292 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
293 /** Demand misses that hit in the MSHRs. */
294 Stats::Formula demandMshrHits;
295 /** Total number of misses that hit in the MSHRs. */
296 Stats::Formula overallMshrHits;
297
298 /** Number of misses that miss in the MSHRs, per command and thread. */
299 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
300 /** Demand misses that miss in the MSHRs. */
301 Stats::Formula demandMshrMisses;
302 /** Total number of misses that miss in the MSHRs. */
303 Stats::Formula overallMshrMisses;
304
305 /** Number of misses that miss in the MSHRs, per command and thread. */
306 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
307 /** Total number of misses that miss in the MSHRs. */
308 Stats::Formula overallMshrUncacheable;
309
310 /** Total cycle latency of each MSHR miss, per command and thread. */
311 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
312 /** Total cycle latency of demand MSHR misses. */
313 Stats::Formula demandMshrMissLatency;
314 /** Total cycle latency of overall MSHR misses. */
315 Stats::Formula overallMshrMissLatency;
316
317 /** Total cycle latency of each MSHR miss, per command and thread. */
318 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
319 /** Total cycle latency of overall MSHR misses. */
320 Stats::Formula overallMshrUncacheableLatency;
321
322 /** The total number of MSHR accesses per command and thread. */
323 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
324 /** The total number of demand MSHR accesses. */
325 Stats::Formula demandMshrAccesses;
326 /** The total number of MSHR accesses. */
327 Stats::Formula overallMshrAccesses;
328
329 /** The miss rate in the MSHRs pre command and thread. */
330 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
331 /** The demand miss rate in the MSHRs. */
332 Stats::Formula demandMshrMissRate;
333 /** The overall miss rate in the MSHRs. */
334 Stats::Formula overallMshrMissRate;
335
336 /** The average latency of an MSHR miss, per command and thread. */
337 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
338 /** The average latency of a demand MSHR miss. */
339 Stats::Formula demandAvgMshrMissLatency;
340 /** The average overall latency of an MSHR miss. */
341 Stats::Formula overallAvgMshrMissLatency;
342
343 /** The average latency of an MSHR miss, per command and thread. */
344 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
345 /** The average overall latency of an MSHR miss. */
346 Stats::Formula overallAvgMshrUncacheableLatency;
347
348 /** The number of times a thread hit its MSHR cap. */
349 Stats::Vector mshr_cap_events;
350 /** The number of times software prefetches caused the MSHR to block. */
351 Stats::Vector soft_prefetch_mshr_full;
352
353 Stats::Scalar mshr_no_allocate_misses;
354
355 /**
356 * @}
357 */
358
359 /**
360 * Register stats for this object.
361 */
362 virtual void regStats();
363
364 public:
365 typedef BaseCacheParams Params;
366 BaseCache(const Params *p);
367 ~BaseCache() {}
368
369 virtual void init();
370
371 /**
372 * Query block size of a cache.
373 * @return The block size
374 */
375 unsigned
376 getBlockSize() const
377 {
378 return blkSize;
379 }
380
381
382 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
383
384
385 const Range<Addr> &getAddrRange() const { return addrRange; }
386
387 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
388 {
389 assert(!pkt->req->isUncacheable());
390 return allocateBufferInternal(&mshrQueue,
391 blockAlign(pkt->getAddr()), blkSize,
392 pkt, time, requestBus);
393 }
394
395 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
396 {
397 assert(pkt->isWrite() && !pkt->isRead());
398 return allocateBufferInternal(&writeBuffer,
399 pkt->getAddr(), pkt->getSize(),
400 pkt, time, requestBus);
401 }
402
403 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
404 {
405 assert(pkt->req->isUncacheable());
406 assert(pkt->isRead());
407 return allocateBufferInternal(&mshrQueue,
408 pkt->getAddr(), pkt->getSize(),
409 pkt, time, requestBus);
410 }
411
412 /**
413 * Returns true if the cache is blocked for accesses.
414 */
415 bool isBlocked()
416 {
417 return blocked != 0;
418 }
419
420 /**
421 * Marks the access path of the cache as blocked for the given cause. This
422 * also sets the blocked flag in the slave interface.
423 * @param cause The reason for the cache blocking.
424 */
425 void setBlocked(BlockedCause cause)
426 {
427 uint8_t flag = 1 << cause;
428 if (blocked == 0) {
429 blocked_causes[cause]++;
430 blockedCycle = curTick;
431 cpuSidePort->setBlocked();
432 }
433 blocked |= flag;
434 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
435 }
436
437 /**
438 * Marks the cache as unblocked for the given cause. This also clears the
439 * blocked flags in the appropriate interfaces.
440 * @param cause The newly unblocked cause.
441 * @warning Calling this function can cause a blocked request on the bus to
442 * access the cache. The cache must be in a state to handle that request.
443 */
444 void clearBlocked(BlockedCause cause)
445 {
446 uint8_t flag = 1 << cause;
447 blocked &= ~flag;
448 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
449 if (blocked == 0) {
450 blocked_cycles[cause] += curTick - blockedCycle;
451 cpuSidePort->clearBlocked();
452 }
453 }
454
455 /**
456 * Request the master bus for the given cause and time.
457 * @param cause The reason for the request.
458 * @param time The time to make the request.
459 */
460 void requestMemSideBus(RequestCause cause, Tick time)
461 {
462 memSidePort->requestBus(cause, time);
463 }
464
465 /**
466 * Clear the master bus request for the given cause.
467 * @param cause The request reason to clear.
468 */
469 void deassertMemSideBusRequest(RequestCause cause)
470 {
471 // Obsolete... we no longer signal bus requests explicitly so
472 // we can't deassert them. Leaving this in as a no-op since
473 // the prefetcher calls it to indicate that it no longer wants
474 // to request a prefetch, and someday that might be
475 // interesting again.
476 }
477
478 virtual unsigned int drain(Event *de);
479
480 virtual bool inCache(Addr addr) = 0;
481
482 virtual bool inMissQueue(Addr addr) = 0;
483
| 228 // Statistics
229 /**
230 * @addtogroup CacheStatistics
231 * @{
232 */
233
234 /** Number of hits per thread for each type of command. @sa Packet::Command */
235 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
236 /** Number of hits for demand accesses. */
237 Stats::Formula demandHits;
238 /** Number of hit for all accesses. */
239 Stats::Formula overallHits;
240
241 /** Number of misses per thread for each type of command. @sa Packet::Command */
242 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
243 /** Number of misses for demand accesses. */
244 Stats::Formula demandMisses;
245 /** Number of misses for all accesses. */
246 Stats::Formula overallMisses;
247
248 /**
249 * Total number of cycles per thread/command spent waiting for a miss.
250 * Used to calculate the average miss latency.
251 */
252 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
253 /** Total number of cycles spent waiting for demand misses. */
254 Stats::Formula demandMissLatency;
255 /** Total number of cycles spent waiting for all misses. */
256 Stats::Formula overallMissLatency;
257
258 /** The number of accesses per command and thread. */
259 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
260 /** The number of demand accesses. */
261 Stats::Formula demandAccesses;
262 /** The number of overall accesses. */
263 Stats::Formula overallAccesses;
264
265 /** The miss rate per command and thread. */
266 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
267 /** The miss rate of all demand accesses. */
268 Stats::Formula demandMissRate;
269 /** The miss rate for all accesses. */
270 Stats::Formula overallMissRate;
271
272 /** The average miss latency per command and thread. */
273 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
274 /** The average miss latency for demand misses. */
275 Stats::Formula demandAvgMissLatency;
276 /** The average miss latency for all misses. */
277 Stats::Formula overallAvgMissLatency;
278
279 /** The total number of cycles blocked for each blocked cause. */
280 Stats::Vector blocked_cycles;
281 /** The number of times this cache blocked for each blocked cause. */
282 Stats::Vector blocked_causes;
283
284 /** The average number of cycles blocked for each blocked cause. */
285 Stats::Formula avg_blocked;
286
287 /** The number of fast writes (WH64) performed. */
288 Stats::Scalar fastWrites;
289
290 /** The number of cache copies performed. */
291 Stats::Scalar cacheCopies;
292
293 /** Number of blocks written back per thread. */
294 Stats::Vector writebacks;
295
296 /** Number of misses that hit in the MSHRs per command and thread. */
297 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
298 /** Demand misses that hit in the MSHRs. */
299 Stats::Formula demandMshrHits;
300 /** Total number of misses that hit in the MSHRs. */
301 Stats::Formula overallMshrHits;
302
303 /** Number of misses that miss in the MSHRs, per command and thread. */
304 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
305 /** Demand misses that miss in the MSHRs. */
306 Stats::Formula demandMshrMisses;
307 /** Total number of misses that miss in the MSHRs. */
308 Stats::Formula overallMshrMisses;
309
310 /** Number of misses that miss in the MSHRs, per command and thread. */
311 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
312 /** Total number of misses that miss in the MSHRs. */
313 Stats::Formula overallMshrUncacheable;
314
315 /** Total cycle latency of each MSHR miss, per command and thread. */
316 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
317 /** Total cycle latency of demand MSHR misses. */
318 Stats::Formula demandMshrMissLatency;
319 /** Total cycle latency of overall MSHR misses. */
320 Stats::Formula overallMshrMissLatency;
321
322 /** Total cycle latency of each MSHR miss, per command and thread. */
323 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
324 /** Total cycle latency of overall MSHR misses. */
325 Stats::Formula overallMshrUncacheableLatency;
326
327 /** The total number of MSHR accesses per command and thread. */
328 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
329 /** The total number of demand MSHR accesses. */
330 Stats::Formula demandMshrAccesses;
331 /** The total number of MSHR accesses. */
332 Stats::Formula overallMshrAccesses;
333
334 /** The miss rate in the MSHRs pre command and thread. */
335 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
336 /** The demand miss rate in the MSHRs. */
337 Stats::Formula demandMshrMissRate;
338 /** The overall miss rate in the MSHRs. */
339 Stats::Formula overallMshrMissRate;
340
341 /** The average latency of an MSHR miss, per command and thread. */
342 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
343 /** The average latency of a demand MSHR miss. */
344 Stats::Formula demandAvgMshrMissLatency;
345 /** The average overall latency of an MSHR miss. */
346 Stats::Formula overallAvgMshrMissLatency;
347
348 /** The average latency of an MSHR miss, per command and thread. */
349 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
350 /** The average overall latency of an MSHR miss. */
351 Stats::Formula overallAvgMshrUncacheableLatency;
352
353 /** The number of times a thread hit its MSHR cap. */
354 Stats::Vector mshr_cap_events;
355 /** The number of times software prefetches caused the MSHR to block. */
356 Stats::Vector soft_prefetch_mshr_full;
357
358 Stats::Scalar mshr_no_allocate_misses;
359
360 /**
361 * @}
362 */
363
364 /**
365 * Register stats for this object.
366 */
367 virtual void regStats();
368
369 public:
370 typedef BaseCacheParams Params;
371 BaseCache(const Params *p);
372 ~BaseCache() {}
373
374 virtual void init();
375
376 /**
377 * Query block size of a cache.
378 * @return The block size
379 */
380 unsigned
381 getBlockSize() const
382 {
383 return blkSize;
384 }
385
386
387 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
388
389
390 const Range<Addr> &getAddrRange() const { return addrRange; }
391
392 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
393 {
394 assert(!pkt->req->isUncacheable());
395 return allocateBufferInternal(&mshrQueue,
396 blockAlign(pkt->getAddr()), blkSize,
397 pkt, time, requestBus);
398 }
399
400 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
401 {
402 assert(pkt->isWrite() && !pkt->isRead());
403 return allocateBufferInternal(&writeBuffer,
404 pkt->getAddr(), pkt->getSize(),
405 pkt, time, requestBus);
406 }
407
408 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
409 {
410 assert(pkt->req->isUncacheable());
411 assert(pkt->isRead());
412 return allocateBufferInternal(&mshrQueue,
413 pkt->getAddr(), pkt->getSize(),
414 pkt, time, requestBus);
415 }
416
417 /**
418 * Returns true if the cache is blocked for accesses.
419 */
420 bool isBlocked()
421 {
422 return blocked != 0;
423 }
424
425 /**
426 * Marks the access path of the cache as blocked for the given cause. This
427 * also sets the blocked flag in the slave interface.
428 * @param cause The reason for the cache blocking.
429 */
430 void setBlocked(BlockedCause cause)
431 {
432 uint8_t flag = 1 << cause;
433 if (blocked == 0) {
434 blocked_causes[cause]++;
435 blockedCycle = curTick;
436 cpuSidePort->setBlocked();
437 }
438 blocked |= flag;
439 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
440 }
441
442 /**
443 * Marks the cache as unblocked for the given cause. This also clears the
444 * blocked flags in the appropriate interfaces.
445 * @param cause The newly unblocked cause.
446 * @warning Calling this function can cause a blocked request on the bus to
447 * access the cache. The cache must be in a state to handle that request.
448 */
449 void clearBlocked(BlockedCause cause)
450 {
451 uint8_t flag = 1 << cause;
452 blocked &= ~flag;
453 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
454 if (blocked == 0) {
455 blocked_cycles[cause] += curTick - blockedCycle;
456 cpuSidePort->clearBlocked();
457 }
458 }
459
460 /**
461 * Request the master bus for the given cause and time.
462 * @param cause The reason for the request.
463 * @param time The time to make the request.
464 */
465 void requestMemSideBus(RequestCause cause, Tick time)
466 {
467 memSidePort->requestBus(cause, time);
468 }
469
470 /**
471 * Clear the master bus request for the given cause.
472 * @param cause The request reason to clear.
473 */
474 void deassertMemSideBusRequest(RequestCause cause)
475 {
476 // Obsolete... we no longer signal bus requests explicitly so
477 // we can't deassert them. Leaving this in as a no-op since
478 // the prefetcher calls it to indicate that it no longer wants
479 // to request a prefetch, and someday that might be
480 // interesting again.
481 }
482
483 virtual unsigned int drain(Event *de);
484
485 virtual bool inCache(Addr addr) = 0;
486
487 virtual bool inMissQueue(Addr addr) = 0;
488
|
484 void incMissCount(PacketPtr pkt)
| 489 void incMissCount(PacketPtr pkt, int id)
|
485 {
| 490 {
|
486 misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++;
| |
487
| 491
|
| 492 if (pkt->cmd == MemCmd::Writeback) {
493 assert(id == -1);
494 misses[pkt->cmdToIndex()][0]++;
495 /* same thing for writeback hits as misses - no context id
496 * available, meanwhile writeback hit/miss stats are not used
497 * in any aggregate hit/miss calculations, so just lump them all
498 * in bucket 0 */
499#if FULL_SYSTEM
500 } else if (id == -1) {
501 // Device accesses have id -1
502 // lump device accesses into their own bucket
503 misses[pkt->cmdToIndex()][_numCpus]++;
504#endif
505 } else {
506 misses[pkt->cmdToIndex()][id % _numCpus]++;
507 }
508
|
488 if (missCount) {
489 --missCount;
490 if (missCount == 0)
491 exitSimLoop("A cache reached the maximum miss count");
492 }
493 }
| 509 if (missCount) {
510 --missCount;
511 if (missCount == 0)
512 exitSimLoop("A cache reached the maximum miss count");
513 }
514 }
|
| 515 void incHitCount(PacketPtr pkt, int id)
516 {
|
494
| 517
|
| 518 /* Writeback requests don't have a context id associated with
519 * them, so attributing a hit to a -1 context id is obviously a
520 * problem. I've noticed in the stats that hits are split into
521 * demand and non-demand hits - neither of which include writeback
522 * hits, so here, I'll just put the writeback hits into bucket 0
523 * since it won't mess with any other stats -hsul */
524 if (pkt->cmd == MemCmd::Writeback) {
525 assert(id == -1);
526 hits[pkt->cmdToIndex()][0]++;
527#if FULL_SYSTEM
528 } else if (id == -1) {
529 // Device accesses have id -1
530 // lump device accesses into their own bucket
531 hits[pkt->cmdToIndex()][_numCpus]++;
532#endif
533 } else {
534 /* the % is necessary in case there are switch cpus */
535 hits[pkt->cmdToIndex()][id % _numCpus]++;
536 }
537 }
538
|
495};
496
497#endif //__BASE_CACHE_HH__
| 539};
540
541#endif //__BASE_CACHE_HH__
|