1/* 2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Steve Reinhardt 42 * Ron Dreslinski 43 */ 44 45/** 46 * @file 47 * Declares a basic cache interface BaseCache. 48 */ 49 50#ifndef __MEM_CACHE_BASE_HH__ 51#define __MEM_CACHE_BASE_HH__ 52 53#include <algorithm> 54#include <list> 55#include <string> 56#include <vector> 57 58#include "base/misc.hh" 59#include "base/statistics.hh" 60#include "base/trace.hh" 61#include "base/types.hh" 62#include "debug/Cache.hh" 63#include "debug/CachePort.hh" 64#include "mem/cache/mshr_queue.hh" 65#include "mem/cache/write_queue.hh" 66#include "mem/mem_object.hh" 67#include "mem/packet.hh" 68#include "mem/qport.hh" 69#include "mem/request.hh" 70#include "params/BaseCache.hh" 71#include "sim/eventq.hh" 72#include "sim/full_system.hh" 73#include "sim/sim_exit.hh" 74#include "sim/system.hh" 75 76/** 77 * A basic cache interface. Implements some common functions for speed. 78 */ 79class BaseCache : public MemObject 80{ 81 protected: 82 /** 83 * Indexes to enumerate the MSHR queues. 84 */ 85 enum MSHRQueueIndex { 86 MSHRQueue_MSHRs, 87 MSHRQueue_WriteBuffer 88 }; 89 90 public: 91 /** 92 * Reasons for caches to be blocked. 93 */ 94 enum BlockedCause { 95 Blocked_NoMSHRs = MSHRQueue_MSHRs, 96 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 97 Blocked_NoTargets, 98 NUM_BLOCKED_CAUSES 99 }; 100 101 protected: 102 103 /** 104 * A cache master port is used for the memory-side port of the 105 * cache, and in addition to the basic timing port that only sends 106 * response packets through a transmit list, it also offers the 107 * ability to schedule and send request packets (requests & 108 * writebacks). The send event is scheduled through schedSendEvent, 109 * and the sendDeferredPacket of the timing port is modified to 110 * consider both the transmit list and the requests from the MSHR. 111 */ 112 class CacheMasterPort : public QueuedMasterPort 113 { 114 115 public: 116 117 /** 118 * Schedule a send of a request packet (from the MSHR). Note 119 * that we could already have a retry outstanding. 120 */ 121 void schedSendEvent(Tick time) 122 { 123 DPRINTF(CachePort, "Scheduling send event at %llu\n", time); 124 reqQueue.schedSendEvent(time); 125 } 126 127 protected: 128 129 CacheMasterPort(const std::string &_name, BaseCache *_cache, 130 ReqPacketQueue &_reqQueue, 131 SnoopRespPacketQueue &_snoopRespQueue) : 132 QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue) 133 { } 134 135 /** 136 * Memory-side port always snoops. 137 * 138 * @return always true 139 */ 140 virtual bool isSnooping() const { return true; } 141 }; 142 143 /** 144 * A cache slave port is used for the CPU-side port of the cache, 145 * and it is basically a simple timing port that uses a transmit 146 * list for responses to the CPU (or connected master). In 147 * addition, it has the functionality to block the port for 148 * incoming requests. If blocked, the port will issue a retry once 149 * unblocked. 150 */ 151 class CacheSlavePort : public QueuedSlavePort 152 { 153 154 public: 155 156 /** Do not accept any new requests. */ 157 void setBlocked(); 158 159 /** Return to normal operation and accept new requests. */ 160 void clearBlocked(); 161 162 bool isBlocked() const { return blocked; } 163 164 protected: 165 166 CacheSlavePort(const std::string &_name, BaseCache *_cache, 167 const std::string &_label); 168 169 /** A normal packet queue used to store responses. */ 170 RespPacketQueue queue; 171 172 bool blocked; 173 174 bool mustSendRetry; 175 176 private: 177 178 void processSendRetry(); 179 180 EventWrapper<CacheSlavePort, 181 &CacheSlavePort::processSendRetry> sendRetryEvent; 182 183 }; 184 185 CacheSlavePort *cpuSidePort; 186 CacheMasterPort *memSidePort; 187 188 protected: 189 190 /** Miss status registers */ 191 MSHRQueue mshrQueue; 192 193 /** Write/writeback buffer */ 194 WriteQueue writeBuffer; 195 196 /** 197 * Mark a request as in service (sent downstream in the memory 198 * system), effectively making this MSHR the ordering point. 199 */ 200 void markInService(MSHR *mshr, bool pending_modified_resp) 201 { 202 bool wasFull = mshrQueue.isFull(); 203 mshrQueue.markInService(mshr, pending_modified_resp); 204 205 if (wasFull && !mshrQueue.isFull()) { 206 clearBlocked(Blocked_NoMSHRs); 207 } 208 } 209 210 void markInService(WriteQueueEntry *entry) 211 { 212 bool wasFull = writeBuffer.isFull(); 213 writeBuffer.markInService(entry); 214 215 if (wasFull && !writeBuffer.isFull()) { 216 clearBlocked(Blocked_NoWBBuffers); 217 } 218 } 219 220 /** 221 * Determine if we should allocate on a fill or not. 222 * 223 * @param cmd Packet command being added as an MSHR target 224 * 225 * @return Whether we should allocate on a fill or not 226 */ 227 virtual bool allocOnFill(MemCmd cmd) const = 0; 228 229 /** 230 * Write back dirty blocks in the cache using functional accesses. 231 */ 232 virtual void memWriteback() = 0; 233 /** 234 * Invalidates all blocks in the cache. 235 * 236 * @warn Dirty cache lines will not be written back to 237 * memory. Make sure to call functionalWriteback() first if you 238 * want the to write them to memory. 239 */ 240 virtual void memInvalidate() = 0; 241 /** 242 * Determine if there are any dirty blocks in the cache. 243 * 244 * \return true if at least one block is dirty, false otherwise. 245 */ 246 virtual bool isDirty() const = 0; 247 248 /** 249 * Determine if an address is in the ranges covered by this 250 * cache. This is useful to filter snoops. 251 * 252 * @param addr Address to check against 253 * 254 * @return If the address in question is in range 255 */ 256 bool inRange(Addr addr) const; 257 258 /** Block size of this cache */ 259 const unsigned blkSize; 260 261 /** 262 * The latency of tag lookup of a cache. It occurs when there is 263 * an access to the cache. 264 */ 265 const Cycles lookupLatency; 266 267 /** 268 * The latency of data access of a cache. It occurs when there is 269 * an access to the cache. 270 */ 271 const Cycles dataLatency; 272 273 /** 274 * This is the forward latency of the cache. It occurs when there 275 * is a cache miss and a request is forwarded downstream, in 276 * particular an outbound miss. 277 */ 278 const Cycles forwardLatency; 279 280 /** The latency to fill a cache block */ 281 const Cycles fillLatency; 282 283 /** 284 * The latency of sending reponse to its upper level cache/core on 285 * a linefill. The responseLatency parameter captures this 286 * latency. 287 */ 288 const Cycles responseLatency; 289 290 /** The number of targets for each MSHR. */ 291 const int numTarget; 292 293 /** Do we forward snoops from mem side port through to cpu side port? */ 294 bool forwardSnoops; 295 296 /** 297 * Is this cache read only, for example the instruction cache, or 298 * table-walker cache. A cache that is read only should never see 299 * any writes, and should never get any dirty data (and hence 300 * never have to do any writebacks). 301 */ 302 const bool isReadOnly; 303 304 /** 305 * Bit vector of the blocking reasons for the access path. 306 * @sa #BlockedCause 307 */ 308 uint8_t blocked; 309 310 /** Increasing order number assigned to each incoming request. */ 311 uint64_t order; 312 313 /** Stores time the cache blocked for statistics. */ 314 Cycles blockedCycle; 315 316 /** Pointer to the MSHR that has no targets. */ 317 MSHR *noTargetMSHR; 318 319 /** The number of misses to trigger an exit event. */ 320 Counter missCount; 321 322 /** 323 * The address range to which the cache responds on the CPU side. 324 * Normally this is all possible memory addresses. */ 325 const AddrRangeList addrRanges; 326 327 public: 328 /** System we are currently operating in. */ 329 System *system; 330 331 // Statistics 332 /** 333 * @addtogroup CacheStatistics 334 * @{ 335 */ 336 337 /** Number of hits per thread for each type of command. 338 @sa Packet::Command */ 339 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 340 /** Number of hits for demand accesses. */ 341 Stats::Formula demandHits; 342 /** Number of hit for all accesses. */ 343 Stats::Formula overallHits; 344 345 /** Number of misses per thread for each type of command. 346 @sa Packet::Command */ 347 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 348 /** Number of misses for demand accesses. */ 349 Stats::Formula demandMisses; 350 /** Number of misses for all accesses. */ 351 Stats::Formula overallMisses; 352 353 /** 354 * Total number of cycles per thread/command spent waiting for a miss. 355 * Used to calculate the average miss latency. 356 */ 357 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 358 /** Total number of cycles spent waiting for demand misses. */ 359 Stats::Formula demandMissLatency; 360 /** Total number of cycles spent waiting for all misses. */ 361 Stats::Formula overallMissLatency; 362 363 /** The number of accesses per command and thread. */ 364 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 365 /** The number of demand accesses. */ 366 Stats::Formula demandAccesses; 367 /** The number of overall accesses. */ 368 Stats::Formula overallAccesses; 369 370 /** The miss rate per command and thread. */ 371 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 372 /** The miss rate of all demand accesses. */ 373 Stats::Formula demandMissRate; 374 /** The miss rate for all accesses. */ 375 Stats::Formula overallMissRate; 376 377 /** The average miss latency per command and thread. */ 378 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 379 /** The average miss latency for demand misses. */ 380 Stats::Formula demandAvgMissLatency; 381 /** The average miss latency for all misses. */ 382 Stats::Formula overallAvgMissLatency; 383 384 /** The total number of cycles blocked for each blocked cause. */ 385 Stats::Vector blocked_cycles; 386 /** The number of times this cache blocked for each blocked cause. */ 387 Stats::Vector blocked_causes; 388 389 /** The average number of cycles blocked for each blocked cause. */ 390 Stats::Formula avg_blocked; 391 392 /** The number of times a HW-prefetched block is evicted w/o reference. */ 393 Stats::Scalar unusedPrefetches; 394 395 /** Number of blocks written back per thread. */ 396 Stats::Vector writebacks; 397 398 /** Number of misses that hit in the MSHRs per command and thread. */ 399 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 400 /** Demand misses that hit in the MSHRs. */ 401 Stats::Formula demandMshrHits; 402 /** Total number of misses that hit in the MSHRs. */ 403 Stats::Formula overallMshrHits; 404 405 /** Number of misses that miss in the MSHRs, per command and thread. */ 406 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 407 /** Demand misses that miss in the MSHRs. */ 408 Stats::Formula demandMshrMisses; 409 /** Total number of misses that miss in the MSHRs. */ 410 Stats::Formula overallMshrMisses; 411 412 /** Number of misses that miss in the MSHRs, per command and thread. */ 413 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 414 /** Total number of misses that miss in the MSHRs. */ 415 Stats::Formula overallMshrUncacheable; 416 417 /** Total cycle latency of each MSHR miss, per command and thread. */ 418 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 419 /** Total cycle latency of demand MSHR misses. */ 420 Stats::Formula demandMshrMissLatency; 421 /** Total cycle latency of overall MSHR misses. */ 422 Stats::Formula overallMshrMissLatency; 423 424 /** Total cycle latency of each MSHR miss, per command and thread. */ 425 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 426 /** Total cycle latency of overall MSHR misses. */ 427 Stats::Formula overallMshrUncacheableLatency; 428 429#if 0 430 /** The total number of MSHR accesses per command and thread. */ 431 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 432 /** The total number of demand MSHR accesses. */ 433 Stats::Formula demandMshrAccesses; 434 /** The total number of MSHR accesses. */ 435 Stats::Formula overallMshrAccesses; 436#endif 437 438 /** The miss rate in the MSHRs pre command and thread. */ 439 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 440 /** The demand miss rate in the MSHRs. */ 441 Stats::Formula demandMshrMissRate; 442 /** The overall miss rate in the MSHRs. */ 443 Stats::Formula overallMshrMissRate; 444 445 /** The average latency of an MSHR miss, per command and thread. */ 446 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 447 /** The average latency of a demand MSHR miss. */ 448 Stats::Formula demandAvgMshrMissLatency; 449 /** The average overall latency of an MSHR miss. */ 450 Stats::Formula overallAvgMshrMissLatency; 451 452 /** The average latency of an MSHR miss, per command and thread. */ 453 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 454 /** The average overall latency of an MSHR miss. */ 455 Stats::Formula overallAvgMshrUncacheableLatency; 456 457 /** 458 * @} 459 */ 460 461 /** 462 * Register stats for this object. 463 */ 464 virtual void regStats(); 465 466 public: 467 BaseCache(const BaseCacheParams *p, unsigned blk_size); 468 ~BaseCache() {} 469 470 virtual void init(); 471 472 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 473 PortID idx = InvalidPortID); 474 virtual BaseSlavePort &getSlavePort(const std::string &if_name, 475 PortID idx = InvalidPortID); 476 477 /** 478 * Query block size of a cache. 479 * @return The block size 480 */ 481 unsigned 482 getBlockSize() const 483 { 484 return blkSize; 485 } 486
| 1/* 2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Erik Hallnor 41 * Steve Reinhardt 42 * Ron Dreslinski 43 */ 44 45/** 46 * @file 47 * Declares a basic cache interface BaseCache. 48 */ 49 50#ifndef __MEM_CACHE_BASE_HH__ 51#define __MEM_CACHE_BASE_HH__ 52 53#include <algorithm> 54#include <list> 55#include <string> 56#include <vector> 57 58#include "base/misc.hh" 59#include "base/statistics.hh" 60#include "base/trace.hh" 61#include "base/types.hh" 62#include "debug/Cache.hh" 63#include "debug/CachePort.hh" 64#include "mem/cache/mshr_queue.hh" 65#include "mem/cache/write_queue.hh" 66#include "mem/mem_object.hh" 67#include "mem/packet.hh" 68#include "mem/qport.hh" 69#include "mem/request.hh" 70#include "params/BaseCache.hh" 71#include "sim/eventq.hh" 72#include "sim/full_system.hh" 73#include "sim/sim_exit.hh" 74#include "sim/system.hh" 75 76/** 77 * A basic cache interface. Implements some common functions for speed. 78 */ 79class BaseCache : public MemObject 80{ 81 protected: 82 /** 83 * Indexes to enumerate the MSHR queues. 84 */ 85 enum MSHRQueueIndex { 86 MSHRQueue_MSHRs, 87 MSHRQueue_WriteBuffer 88 }; 89 90 public: 91 /** 92 * Reasons for caches to be blocked. 93 */ 94 enum BlockedCause { 95 Blocked_NoMSHRs = MSHRQueue_MSHRs, 96 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer, 97 Blocked_NoTargets, 98 NUM_BLOCKED_CAUSES 99 }; 100 101 protected: 102 103 /** 104 * A cache master port is used for the memory-side port of the 105 * cache, and in addition to the basic timing port that only sends 106 * response packets through a transmit list, it also offers the 107 * ability to schedule and send request packets (requests & 108 * writebacks). The send event is scheduled through schedSendEvent, 109 * and the sendDeferredPacket of the timing port is modified to 110 * consider both the transmit list and the requests from the MSHR. 111 */ 112 class CacheMasterPort : public QueuedMasterPort 113 { 114 115 public: 116 117 /** 118 * Schedule a send of a request packet (from the MSHR). Note 119 * that we could already have a retry outstanding. 120 */ 121 void schedSendEvent(Tick time) 122 { 123 DPRINTF(CachePort, "Scheduling send event at %llu\n", time); 124 reqQueue.schedSendEvent(time); 125 } 126 127 protected: 128 129 CacheMasterPort(const std::string &_name, BaseCache *_cache, 130 ReqPacketQueue &_reqQueue, 131 SnoopRespPacketQueue &_snoopRespQueue) : 132 QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue) 133 { } 134 135 /** 136 * Memory-side port always snoops. 137 * 138 * @return always true 139 */ 140 virtual bool isSnooping() const { return true; } 141 }; 142 143 /** 144 * A cache slave port is used for the CPU-side port of the cache, 145 * and it is basically a simple timing port that uses a transmit 146 * list for responses to the CPU (or connected master). In 147 * addition, it has the functionality to block the port for 148 * incoming requests. If blocked, the port will issue a retry once 149 * unblocked. 150 */ 151 class CacheSlavePort : public QueuedSlavePort 152 { 153 154 public: 155 156 /** Do not accept any new requests. */ 157 void setBlocked(); 158 159 /** Return to normal operation and accept new requests. */ 160 void clearBlocked(); 161 162 bool isBlocked() const { return blocked; } 163 164 protected: 165 166 CacheSlavePort(const std::string &_name, BaseCache *_cache, 167 const std::string &_label); 168 169 /** A normal packet queue used to store responses. */ 170 RespPacketQueue queue; 171 172 bool blocked; 173 174 bool mustSendRetry; 175 176 private: 177 178 void processSendRetry(); 179 180 EventWrapper<CacheSlavePort, 181 &CacheSlavePort::processSendRetry> sendRetryEvent; 182 183 }; 184 185 CacheSlavePort *cpuSidePort; 186 CacheMasterPort *memSidePort; 187 188 protected: 189 190 /** Miss status registers */ 191 MSHRQueue mshrQueue; 192 193 /** Write/writeback buffer */ 194 WriteQueue writeBuffer; 195 196 /** 197 * Mark a request as in service (sent downstream in the memory 198 * system), effectively making this MSHR the ordering point. 199 */ 200 void markInService(MSHR *mshr, bool pending_modified_resp) 201 { 202 bool wasFull = mshrQueue.isFull(); 203 mshrQueue.markInService(mshr, pending_modified_resp); 204 205 if (wasFull && !mshrQueue.isFull()) { 206 clearBlocked(Blocked_NoMSHRs); 207 } 208 } 209 210 void markInService(WriteQueueEntry *entry) 211 { 212 bool wasFull = writeBuffer.isFull(); 213 writeBuffer.markInService(entry); 214 215 if (wasFull && !writeBuffer.isFull()) { 216 clearBlocked(Blocked_NoWBBuffers); 217 } 218 } 219 220 /** 221 * Determine if we should allocate on a fill or not. 222 * 223 * @param cmd Packet command being added as an MSHR target 224 * 225 * @return Whether we should allocate on a fill or not 226 */ 227 virtual bool allocOnFill(MemCmd cmd) const = 0; 228 229 /** 230 * Write back dirty blocks in the cache using functional accesses. 231 */ 232 virtual void memWriteback() = 0; 233 /** 234 * Invalidates all blocks in the cache. 235 * 236 * @warn Dirty cache lines will not be written back to 237 * memory. Make sure to call functionalWriteback() first if you 238 * want the to write them to memory. 239 */ 240 virtual void memInvalidate() = 0; 241 /** 242 * Determine if there are any dirty blocks in the cache. 243 * 244 * \return true if at least one block is dirty, false otherwise. 245 */ 246 virtual bool isDirty() const = 0; 247 248 /** 249 * Determine if an address is in the ranges covered by this 250 * cache. This is useful to filter snoops. 251 * 252 * @param addr Address to check against 253 * 254 * @return If the address in question is in range 255 */ 256 bool inRange(Addr addr) const; 257 258 /** Block size of this cache */ 259 const unsigned blkSize; 260 261 /** 262 * The latency of tag lookup of a cache. It occurs when there is 263 * an access to the cache. 264 */ 265 const Cycles lookupLatency; 266 267 /** 268 * The latency of data access of a cache. It occurs when there is 269 * an access to the cache. 270 */ 271 const Cycles dataLatency; 272 273 /** 274 * This is the forward latency of the cache. It occurs when there 275 * is a cache miss and a request is forwarded downstream, in 276 * particular an outbound miss. 277 */ 278 const Cycles forwardLatency; 279 280 /** The latency to fill a cache block */ 281 const Cycles fillLatency; 282 283 /** 284 * The latency of sending reponse to its upper level cache/core on 285 * a linefill. The responseLatency parameter captures this 286 * latency. 287 */ 288 const Cycles responseLatency; 289 290 /** The number of targets for each MSHR. */ 291 const int numTarget; 292 293 /** Do we forward snoops from mem side port through to cpu side port? */ 294 bool forwardSnoops; 295 296 /** 297 * Is this cache read only, for example the instruction cache, or 298 * table-walker cache. A cache that is read only should never see 299 * any writes, and should never get any dirty data (and hence 300 * never have to do any writebacks). 301 */ 302 const bool isReadOnly; 303 304 /** 305 * Bit vector of the blocking reasons for the access path. 306 * @sa #BlockedCause 307 */ 308 uint8_t blocked; 309 310 /** Increasing order number assigned to each incoming request. */ 311 uint64_t order; 312 313 /** Stores time the cache blocked for statistics. */ 314 Cycles blockedCycle; 315 316 /** Pointer to the MSHR that has no targets. */ 317 MSHR *noTargetMSHR; 318 319 /** The number of misses to trigger an exit event. */ 320 Counter missCount; 321 322 /** 323 * The address range to which the cache responds on the CPU side. 324 * Normally this is all possible memory addresses. */ 325 const AddrRangeList addrRanges; 326 327 public: 328 /** System we are currently operating in. */ 329 System *system; 330 331 // Statistics 332 /** 333 * @addtogroup CacheStatistics 334 * @{ 335 */ 336 337 /** Number of hits per thread for each type of command. 338 @sa Packet::Command */ 339 Stats::Vector hits[MemCmd::NUM_MEM_CMDS]; 340 /** Number of hits for demand accesses. */ 341 Stats::Formula demandHits; 342 /** Number of hit for all accesses. */ 343 Stats::Formula overallHits; 344 345 /** Number of misses per thread for each type of command. 346 @sa Packet::Command */ 347 Stats::Vector misses[MemCmd::NUM_MEM_CMDS]; 348 /** Number of misses for demand accesses. */ 349 Stats::Formula demandMisses; 350 /** Number of misses for all accesses. */ 351 Stats::Formula overallMisses; 352 353 /** 354 * Total number of cycles per thread/command spent waiting for a miss. 355 * Used to calculate the average miss latency. 356 */ 357 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS]; 358 /** Total number of cycles spent waiting for demand misses. */ 359 Stats::Formula demandMissLatency; 360 /** Total number of cycles spent waiting for all misses. */ 361 Stats::Formula overallMissLatency; 362 363 /** The number of accesses per command and thread. */ 364 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS]; 365 /** The number of demand accesses. */ 366 Stats::Formula demandAccesses; 367 /** The number of overall accesses. */ 368 Stats::Formula overallAccesses; 369 370 /** The miss rate per command and thread. */ 371 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS]; 372 /** The miss rate of all demand accesses. */ 373 Stats::Formula demandMissRate; 374 /** The miss rate for all accesses. */ 375 Stats::Formula overallMissRate; 376 377 /** The average miss latency per command and thread. */ 378 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS]; 379 /** The average miss latency for demand misses. */ 380 Stats::Formula demandAvgMissLatency; 381 /** The average miss latency for all misses. */ 382 Stats::Formula overallAvgMissLatency; 383 384 /** The total number of cycles blocked for each blocked cause. */ 385 Stats::Vector blocked_cycles; 386 /** The number of times this cache blocked for each blocked cause. */ 387 Stats::Vector blocked_causes; 388 389 /** The average number of cycles blocked for each blocked cause. */ 390 Stats::Formula avg_blocked; 391 392 /** The number of times a HW-prefetched block is evicted w/o reference. */ 393 Stats::Scalar unusedPrefetches; 394 395 /** Number of blocks written back per thread. */ 396 Stats::Vector writebacks; 397 398 /** Number of misses that hit in the MSHRs per command and thread. */ 399 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS]; 400 /** Demand misses that hit in the MSHRs. */ 401 Stats::Formula demandMshrHits; 402 /** Total number of misses that hit in the MSHRs. */ 403 Stats::Formula overallMshrHits; 404 405 /** Number of misses that miss in the MSHRs, per command and thread. */ 406 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS]; 407 /** Demand misses that miss in the MSHRs. */ 408 Stats::Formula demandMshrMisses; 409 /** Total number of misses that miss in the MSHRs. */ 410 Stats::Formula overallMshrMisses; 411 412 /** Number of misses that miss in the MSHRs, per command and thread. */ 413 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS]; 414 /** Total number of misses that miss in the MSHRs. */ 415 Stats::Formula overallMshrUncacheable; 416 417 /** Total cycle latency of each MSHR miss, per command and thread. */ 418 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS]; 419 /** Total cycle latency of demand MSHR misses. */ 420 Stats::Formula demandMshrMissLatency; 421 /** Total cycle latency of overall MSHR misses. */ 422 Stats::Formula overallMshrMissLatency; 423 424 /** Total cycle latency of each MSHR miss, per command and thread. */ 425 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS]; 426 /** Total cycle latency of overall MSHR misses. */ 427 Stats::Formula overallMshrUncacheableLatency; 428 429#if 0 430 /** The total number of MSHR accesses per command and thread. */ 431 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS]; 432 /** The total number of demand MSHR accesses. */ 433 Stats::Formula demandMshrAccesses; 434 /** The total number of MSHR accesses. */ 435 Stats::Formula overallMshrAccesses; 436#endif 437 438 /** The miss rate in the MSHRs pre command and thread. */ 439 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS]; 440 /** The demand miss rate in the MSHRs. */ 441 Stats::Formula demandMshrMissRate; 442 /** The overall miss rate in the MSHRs. */ 443 Stats::Formula overallMshrMissRate; 444 445 /** The average latency of an MSHR miss, per command and thread. */ 446 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS]; 447 /** The average latency of a demand MSHR miss. */ 448 Stats::Formula demandAvgMshrMissLatency; 449 /** The average overall latency of an MSHR miss. */ 450 Stats::Formula overallAvgMshrMissLatency; 451 452 /** The average latency of an MSHR miss, per command and thread. */ 453 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS]; 454 /** The average overall latency of an MSHR miss. */ 455 Stats::Formula overallAvgMshrUncacheableLatency; 456 457 /** 458 * @} 459 */ 460 461 /** 462 * Register stats for this object. 463 */ 464 virtual void regStats(); 465 466 public: 467 BaseCache(const BaseCacheParams *p, unsigned blk_size); 468 ~BaseCache() {} 469 470 virtual void init(); 471 472 virtual BaseMasterPort &getMasterPort(const std::string &if_name, 473 PortID idx = InvalidPortID); 474 virtual BaseSlavePort &getSlavePort(const std::string &if_name, 475 PortID idx = InvalidPortID); 476 477 /** 478 * Query block size of a cache. 479 * @return The block size 480 */ 481 unsigned 482 getBlockSize() const 483 { 484 return blkSize; 485 } 486
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517 518 WriteQueueEntry *wq_entry = 519 writeBuffer.findMatch(blk_addr, pkt->isSecure()); 520 if (wq_entry && !wq_entry->inService) { 521 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print()); 522 } 523 524 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++); 525 526 if (writeBuffer.isFull()) { 527 setBlocked((BlockedCause)MSHRQueue_WriteBuffer); 528 } 529 530 // schedule the send 531 schedMemSideSendEvent(time); 532 } 533 534 /** 535 * Returns true if the cache is blocked for accesses. 536 */ 537 bool isBlocked() const 538 { 539 return blocked != 0; 540 } 541 542 /** 543 * Marks the access path of the cache as blocked for the given cause. This 544 * also sets the blocked flag in the slave interface. 545 * @param cause The reason for the cache blocking. 546 */ 547 void setBlocked(BlockedCause cause) 548 { 549 uint8_t flag = 1 << cause; 550 if (blocked == 0) { 551 blocked_causes[cause]++; 552 blockedCycle = curCycle(); 553 cpuSidePort->setBlocked(); 554 } 555 blocked |= flag; 556 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 557 } 558 559 /** 560 * Marks the cache as unblocked for the given cause. This also clears the 561 * blocked flags in the appropriate interfaces. 562 * @param cause The newly unblocked cause. 563 * @warning Calling this function can cause a blocked request on the bus to 564 * access the cache. The cache must be in a state to handle that request. 565 */ 566 void clearBlocked(BlockedCause cause) 567 { 568 uint8_t flag = 1 << cause; 569 blocked &= ~flag; 570 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 571 if (blocked == 0) { 572 blocked_cycles[cause] += curCycle() - blockedCycle; 573 cpuSidePort->clearBlocked(); 574 } 575 } 576 577 /** 578 * Schedule a send event for the memory-side port. If already 579 * scheduled, this may reschedule the event at an earlier 580 * time. When the specified time is reached, the port is free to 581 * send either a response, a request, or a prefetch request. 582 * 583 * @param time The time when to attempt sending a packet. 584 */ 585 void schedMemSideSendEvent(Tick time) 586 { 587 memSidePort->schedSendEvent(time); 588 } 589 590 virtual bool inCache(Addr addr, bool is_secure) const = 0; 591 592 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0; 593 594 void incMissCount(PacketPtr pkt) 595 { 596 assert(pkt->req->masterId() < system->maxMasters()); 597 misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 598 pkt->req->incAccessDepth(); 599 if (missCount) { 600 --missCount; 601 if (missCount == 0) 602 exitSimLoop("A cache reached the maximum miss count"); 603 } 604 } 605 void incHitCount(PacketPtr pkt) 606 { 607 assert(pkt->req->masterId() < system->maxMasters()); 608 hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 609 610 } 611 612}; 613 614#endif //__MEM_CACHE_BASE_HH__
| 513 514 WriteQueueEntry *wq_entry = 515 writeBuffer.findMatch(blk_addr, pkt->isSecure()); 516 if (wq_entry && !wq_entry->inService) { 517 DPRINTF(Cache, "Potential to merge writeback %s", pkt->print()); 518 } 519 520 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++); 521 522 if (writeBuffer.isFull()) { 523 setBlocked((BlockedCause)MSHRQueue_WriteBuffer); 524 } 525 526 // schedule the send 527 schedMemSideSendEvent(time); 528 } 529 530 /** 531 * Returns true if the cache is blocked for accesses. 532 */ 533 bool isBlocked() const 534 { 535 return blocked != 0; 536 } 537 538 /** 539 * Marks the access path of the cache as blocked for the given cause. This 540 * also sets the blocked flag in the slave interface. 541 * @param cause The reason for the cache blocking. 542 */ 543 void setBlocked(BlockedCause cause) 544 { 545 uint8_t flag = 1 << cause; 546 if (blocked == 0) { 547 blocked_causes[cause]++; 548 blockedCycle = curCycle(); 549 cpuSidePort->setBlocked(); 550 } 551 blocked |= flag; 552 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked); 553 } 554 555 /** 556 * Marks the cache as unblocked for the given cause. This also clears the 557 * blocked flags in the appropriate interfaces. 558 * @param cause The newly unblocked cause. 559 * @warning Calling this function can cause a blocked request on the bus to 560 * access the cache. The cache must be in a state to handle that request. 561 */ 562 void clearBlocked(BlockedCause cause) 563 { 564 uint8_t flag = 1 << cause; 565 blocked &= ~flag; 566 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked); 567 if (blocked == 0) { 568 blocked_cycles[cause] += curCycle() - blockedCycle; 569 cpuSidePort->clearBlocked(); 570 } 571 } 572 573 /** 574 * Schedule a send event for the memory-side port. If already 575 * scheduled, this may reschedule the event at an earlier 576 * time. When the specified time is reached, the port is free to 577 * send either a response, a request, or a prefetch request. 578 * 579 * @param time The time when to attempt sending a packet. 580 */ 581 void schedMemSideSendEvent(Tick time) 582 { 583 memSidePort->schedSendEvent(time); 584 } 585 586 virtual bool inCache(Addr addr, bool is_secure) const = 0; 587 588 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0; 589 590 void incMissCount(PacketPtr pkt) 591 { 592 assert(pkt->req->masterId() < system->maxMasters()); 593 misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 594 pkt->req->incAccessDepth(); 595 if (missCount) { 596 --missCount; 597 if (missCount == 0) 598 exitSimLoop("A cache reached the maximum miss count"); 599 } 600 } 601 void incHitCount(PacketPtr pkt) 602 { 603 assert(pkt->req->masterId() < system->maxMasters()); 604 hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 605 606 } 607 608}; 609 610#endif //__MEM_CACHE_BASE_HH__
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