1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __MEM_CACHE_BASE_HH__
51#define __MEM_CACHE_BASE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/cache/write_queue.hh"
66#include "mem/mem_object.hh"
67#include "mem/packet.hh"
68#include "mem/qport.hh"
69#include "mem/request.hh"
70#include "params/BaseCache.hh"
71#include "sim/eventq.hh"
72#include "sim/full_system.hh"
73#include "sim/sim_exit.hh"
74#include "sim/system.hh"
75
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 protected:
82 /**
83 * Indexes to enumerate the MSHR queues.
84 */
85 enum MSHRQueueIndex {
86 MSHRQueue_MSHRs,
87 MSHRQueue_WriteBuffer
88 };
89
90 public:
91 /**
92 * Reasons for caches to be blocked.
93 */
94 enum BlockedCause {
95 Blocked_NoMSHRs = MSHRQueue_MSHRs,
96 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
97 Blocked_NoTargets,
98 NUM_BLOCKED_CAUSES
99 };
100
101 protected:
102
103 /**
104 * A cache master port is used for the memory-side port of the
105 * cache, and in addition to the basic timing port that only sends
106 * response packets through a transmit list, it also offers the
107 * ability to schedule and send request packets (requests &
108 * writebacks). The send event is scheduled through schedSendEvent,
109 * and the sendDeferredPacket of the timing port is modified to
110 * consider both the transmit list and the requests from the MSHR.
111 */
112 class CacheMasterPort : public QueuedMasterPort
113 {
114
115 public:
116
117 /**
118 * Schedule a send of a request packet (from the MSHR). Note
119 * that we could already have a retry outstanding.
120 */
121 void schedSendEvent(Tick time)
122 {
123 DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
124 reqQueue.schedSendEvent(time);
125 }
126
127 protected:
128
129 CacheMasterPort(const std::string &_name, BaseCache *_cache,
130 ReqPacketQueue &_reqQueue,
131 SnoopRespPacketQueue &_snoopRespQueue) :
132 QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
133 { }
134
135 /**
136 * Memory-side port always snoops.
137 *
138 * @return always true
139 */
140 virtual bool isSnooping() const { return true; }
141 };
142
143 /**
144 * A cache slave port is used for the CPU-side port of the cache,
145 * and it is basically a simple timing port that uses a transmit
146 * list for responses to the CPU (or connected master). In
147 * addition, it has the functionality to block the port for
148 * incoming requests. If blocked, the port will issue a retry once
149 * unblocked.
150 */
151 class CacheSlavePort : public QueuedSlavePort
152 {
153
154 public:
155
156 /** Do not accept any new requests. */
157 void setBlocked();
158
159 /** Return to normal operation and accept new requests. */
160 void clearBlocked();
161
162 bool isBlocked() const { return blocked; }
163
164 protected:
165
166 CacheSlavePort(const std::string &_name, BaseCache *_cache,
167 const std::string &_label);
168
169 /** A normal packet queue used to store responses. */
170 RespPacketQueue queue;
171
172 bool blocked;
173
174 bool mustSendRetry;
175
176 private:
177
178 void processSendRetry();
179
180 EventWrapper<CacheSlavePort,
181 &CacheSlavePort::processSendRetry> sendRetryEvent;
182
183 };
184
185 CacheSlavePort *cpuSidePort;
186 CacheMasterPort *memSidePort;
187
188 protected:
189
190 /** Miss status registers */
191 MSHRQueue mshrQueue;
192
193 /** Write/writeback buffer */
194 WriteQueue writeBuffer;
195
196 /**
197 * Mark a request as in service (sent downstream in the memory
198 * system), effectively making this MSHR the ordering point.
199 */
200 void markInService(MSHR *mshr, bool pending_modified_resp)
201 {
202 bool wasFull = mshrQueue.isFull();
203 mshrQueue.markInService(mshr, pending_modified_resp);
204
205 if (wasFull && !mshrQueue.isFull()) {
206 clearBlocked(Blocked_NoMSHRs);
207 }
208 }
209
210 void markInService(WriteQueueEntry *entry)
211 {
212 bool wasFull = writeBuffer.isFull();
213 writeBuffer.markInService(entry);
214
215 if (wasFull && !writeBuffer.isFull()) {
216 clearBlocked(Blocked_NoWBBuffers);
217 }
218 }
219
220 /**
221 * Determine if we should allocate on a fill or not.
222 *
223 * @param cmd Packet command being added as an MSHR target
224 *
225 * @return Whether we should allocate on a fill or not
226 */
227 virtual bool allocOnFill(MemCmd cmd) const = 0;
228
229 /**
230 * Write back dirty blocks in the cache using functional accesses.
231 */
232 virtual void memWriteback() = 0;
233 /**
234 * Invalidates all blocks in the cache.
235 *
236 * @warn Dirty cache lines will not be written back to
237 * memory. Make sure to call functionalWriteback() first if you
238 * want the to write them to memory.
239 */
240 virtual void memInvalidate() = 0;
241 /**
242 * Determine if there are any dirty blocks in the cache.
243 *
244 * \return true if at least one block is dirty, false otherwise.
245 */
246 virtual bool isDirty() const = 0;
247
248 /**
249 * Determine if an address is in the ranges covered by this
250 * cache. This is useful to filter snoops.
251 *
252 * @param addr Address to check against
253 *
254 * @return If the address in question is in range
255 */
256 bool inRange(Addr addr) const;
257
258 /** Block size of this cache */
259 const unsigned blkSize;
260
261 /**
262 * The latency of tag lookup of a cache. It occurs when there is
263 * an access to the cache.
264 */
265 const Cycles lookupLatency;
266
267 /**
268 * This is the forward latency of the cache. It occurs when there
269 * is a cache miss and a request is forwarded downstream, in
270 * particular an outbound miss.
271 */
272 const Cycles forwardLatency;
273
274 /** The latency to fill a cache block */
275 const Cycles fillLatency;
276
277 /**
278 * The latency of sending reponse to its upper level cache/core on
279 * a linefill. The responseLatency parameter captures this
280 * latency.
281 */
282 const Cycles responseLatency;
283
284 /** The number of targets for each MSHR. */
285 const int numTarget;
286
287 /** Do we forward snoops from mem side port through to cpu side port? */
288 bool forwardSnoops;
289
290 /**
291 * Is this cache read only, for example the instruction cache, or
292 * table-walker cache. A cache that is read only should never see
293 * any writes, and should never get any dirty data (and hence
294 * never have to do any writebacks).
295 */
296 const bool isReadOnly;
297
298 /**
299 * Bit vector of the blocking reasons for the access path.
300 * @sa #BlockedCause
301 */
302 uint8_t blocked;
303
304 /** Increasing order number assigned to each incoming request. */
305 uint64_t order;
306
307 /** Stores time the cache blocked for statistics. */
308 Cycles blockedCycle;
309
310 /** Pointer to the MSHR that has no targets. */
311 MSHR *noTargetMSHR;
312
313 /** The number of misses to trigger an exit event. */
314 Counter missCount;
315
316 /**
317 * The address range to which the cache responds on the CPU side.
318 * Normally this is all possible memory addresses. */
319 const AddrRangeList addrRanges;
320
321 public:
322 /** System we are currently operating in. */
323 System *system;
324
325 // Statistics
326 /**
327 * @addtogroup CacheStatistics
328 * @{
329 */
330
| 1/*
2 * Copyright (c) 2012-2013, 2015-2016 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __MEM_CACHE_BASE_HH__
51#define __MEM_CACHE_BASE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/cache/write_queue.hh"
66#include "mem/mem_object.hh"
67#include "mem/packet.hh"
68#include "mem/qport.hh"
69#include "mem/request.hh"
70#include "params/BaseCache.hh"
71#include "sim/eventq.hh"
72#include "sim/full_system.hh"
73#include "sim/sim_exit.hh"
74#include "sim/system.hh"
75
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 protected:
82 /**
83 * Indexes to enumerate the MSHR queues.
84 */
85 enum MSHRQueueIndex {
86 MSHRQueue_MSHRs,
87 MSHRQueue_WriteBuffer
88 };
89
90 public:
91 /**
92 * Reasons for caches to be blocked.
93 */
94 enum BlockedCause {
95 Blocked_NoMSHRs = MSHRQueue_MSHRs,
96 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
97 Blocked_NoTargets,
98 NUM_BLOCKED_CAUSES
99 };
100
101 protected:
102
103 /**
104 * A cache master port is used for the memory-side port of the
105 * cache, and in addition to the basic timing port that only sends
106 * response packets through a transmit list, it also offers the
107 * ability to schedule and send request packets (requests &
108 * writebacks). The send event is scheduled through schedSendEvent,
109 * and the sendDeferredPacket of the timing port is modified to
110 * consider both the transmit list and the requests from the MSHR.
111 */
112 class CacheMasterPort : public QueuedMasterPort
113 {
114
115 public:
116
117 /**
118 * Schedule a send of a request packet (from the MSHR). Note
119 * that we could already have a retry outstanding.
120 */
121 void schedSendEvent(Tick time)
122 {
123 DPRINTF(CachePort, "Scheduling send event at %llu\n", time);
124 reqQueue.schedSendEvent(time);
125 }
126
127 protected:
128
129 CacheMasterPort(const std::string &_name, BaseCache *_cache,
130 ReqPacketQueue &_reqQueue,
131 SnoopRespPacketQueue &_snoopRespQueue) :
132 QueuedMasterPort(_name, _cache, _reqQueue, _snoopRespQueue)
133 { }
134
135 /**
136 * Memory-side port always snoops.
137 *
138 * @return always true
139 */
140 virtual bool isSnooping() const { return true; }
141 };
142
143 /**
144 * A cache slave port is used for the CPU-side port of the cache,
145 * and it is basically a simple timing port that uses a transmit
146 * list for responses to the CPU (or connected master). In
147 * addition, it has the functionality to block the port for
148 * incoming requests. If blocked, the port will issue a retry once
149 * unblocked.
150 */
151 class CacheSlavePort : public QueuedSlavePort
152 {
153
154 public:
155
156 /** Do not accept any new requests. */
157 void setBlocked();
158
159 /** Return to normal operation and accept new requests. */
160 void clearBlocked();
161
162 bool isBlocked() const { return blocked; }
163
164 protected:
165
166 CacheSlavePort(const std::string &_name, BaseCache *_cache,
167 const std::string &_label);
168
169 /** A normal packet queue used to store responses. */
170 RespPacketQueue queue;
171
172 bool blocked;
173
174 bool mustSendRetry;
175
176 private:
177
178 void processSendRetry();
179
180 EventWrapper<CacheSlavePort,
181 &CacheSlavePort::processSendRetry> sendRetryEvent;
182
183 };
184
185 CacheSlavePort *cpuSidePort;
186 CacheMasterPort *memSidePort;
187
188 protected:
189
190 /** Miss status registers */
191 MSHRQueue mshrQueue;
192
193 /** Write/writeback buffer */
194 WriteQueue writeBuffer;
195
196 /**
197 * Mark a request as in service (sent downstream in the memory
198 * system), effectively making this MSHR the ordering point.
199 */
200 void markInService(MSHR *mshr, bool pending_modified_resp)
201 {
202 bool wasFull = mshrQueue.isFull();
203 mshrQueue.markInService(mshr, pending_modified_resp);
204
205 if (wasFull && !mshrQueue.isFull()) {
206 clearBlocked(Blocked_NoMSHRs);
207 }
208 }
209
210 void markInService(WriteQueueEntry *entry)
211 {
212 bool wasFull = writeBuffer.isFull();
213 writeBuffer.markInService(entry);
214
215 if (wasFull && !writeBuffer.isFull()) {
216 clearBlocked(Blocked_NoWBBuffers);
217 }
218 }
219
220 /**
221 * Determine if we should allocate on a fill or not.
222 *
223 * @param cmd Packet command being added as an MSHR target
224 *
225 * @return Whether we should allocate on a fill or not
226 */
227 virtual bool allocOnFill(MemCmd cmd) const = 0;
228
229 /**
230 * Write back dirty blocks in the cache using functional accesses.
231 */
232 virtual void memWriteback() = 0;
233 /**
234 * Invalidates all blocks in the cache.
235 *
236 * @warn Dirty cache lines will not be written back to
237 * memory. Make sure to call functionalWriteback() first if you
238 * want the to write them to memory.
239 */
240 virtual void memInvalidate() = 0;
241 /**
242 * Determine if there are any dirty blocks in the cache.
243 *
244 * \return true if at least one block is dirty, false otherwise.
245 */
246 virtual bool isDirty() const = 0;
247
248 /**
249 * Determine if an address is in the ranges covered by this
250 * cache. This is useful to filter snoops.
251 *
252 * @param addr Address to check against
253 *
254 * @return If the address in question is in range
255 */
256 bool inRange(Addr addr) const;
257
258 /** Block size of this cache */
259 const unsigned blkSize;
260
261 /**
262 * The latency of tag lookup of a cache. It occurs when there is
263 * an access to the cache.
264 */
265 const Cycles lookupLatency;
266
267 /**
268 * This is the forward latency of the cache. It occurs when there
269 * is a cache miss and a request is forwarded downstream, in
270 * particular an outbound miss.
271 */
272 const Cycles forwardLatency;
273
274 /** The latency to fill a cache block */
275 const Cycles fillLatency;
276
277 /**
278 * The latency of sending reponse to its upper level cache/core on
279 * a linefill. The responseLatency parameter captures this
280 * latency.
281 */
282 const Cycles responseLatency;
283
284 /** The number of targets for each MSHR. */
285 const int numTarget;
286
287 /** Do we forward snoops from mem side port through to cpu side port? */
288 bool forwardSnoops;
289
290 /**
291 * Is this cache read only, for example the instruction cache, or
292 * table-walker cache. A cache that is read only should never see
293 * any writes, and should never get any dirty data (and hence
294 * never have to do any writebacks).
295 */
296 const bool isReadOnly;
297
298 /**
299 * Bit vector of the blocking reasons for the access path.
300 * @sa #BlockedCause
301 */
302 uint8_t blocked;
303
304 /** Increasing order number assigned to each incoming request. */
305 uint64_t order;
306
307 /** Stores time the cache blocked for statistics. */
308 Cycles blockedCycle;
309
310 /** Pointer to the MSHR that has no targets. */
311 MSHR *noTargetMSHR;
312
313 /** The number of misses to trigger an exit event. */
314 Counter missCount;
315
316 /**
317 * The address range to which the cache responds on the CPU side.
318 * Normally this is all possible memory addresses. */
319 const AddrRangeList addrRanges;
320
321 public:
322 /** System we are currently operating in. */
323 System *system;
324
325 // Statistics
326 /**
327 * @addtogroup CacheStatistics
328 * @{
329 */
330
|
339 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
340 /** Number of misses for demand accesses. */
341 Stats::Formula demandMisses;
342 /** Number of misses for all accesses. */
343 Stats::Formula overallMisses;
344
345 /**
346 * Total number of cycles per thread/command spent waiting for a miss.
347 * Used to calculate the average miss latency.
348 */
349 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
350 /** Total number of cycles spent waiting for demand misses. */
351 Stats::Formula demandMissLatency;
352 /** Total number of cycles spent waiting for all misses. */
353 Stats::Formula overallMissLatency;
354
355 /** The number of accesses per command and thread. */
356 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
357 /** The number of demand accesses. */
358 Stats::Formula demandAccesses;
359 /** The number of overall accesses. */
360 Stats::Formula overallAccesses;
361
362 /** The miss rate per command and thread. */
363 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
364 /** The miss rate of all demand accesses. */
365 Stats::Formula demandMissRate;
366 /** The miss rate for all accesses. */
367 Stats::Formula overallMissRate;
368
369 /** The average miss latency per command and thread. */
370 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
371 /** The average miss latency for demand misses. */
372 Stats::Formula demandAvgMissLatency;
373 /** The average miss latency for all misses. */
374 Stats::Formula overallAvgMissLatency;
375
376 /** The total number of cycles blocked for each blocked cause. */
377 Stats::Vector blocked_cycles;
378 /** The number of times this cache blocked for each blocked cause. */
379 Stats::Vector blocked_causes;
380
381 /** The average number of cycles blocked for each blocked cause. */
382 Stats::Formula avg_blocked;
383
384 /** The number of times a HW-prefetched block is evicted w/o reference. */
385 Stats::Scalar unusedPrefetches;
386
387 /** Number of blocks written back per thread. */
388 Stats::Vector writebacks;
389
390 /** Number of misses that hit in the MSHRs per command and thread. */
391 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
392 /** Demand misses that hit in the MSHRs. */
393 Stats::Formula demandMshrHits;
394 /** Total number of misses that hit in the MSHRs. */
395 Stats::Formula overallMshrHits;
396
397 /** Number of misses that miss in the MSHRs, per command and thread. */
398 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
399 /** Demand misses that miss in the MSHRs. */
400 Stats::Formula demandMshrMisses;
401 /** Total number of misses that miss in the MSHRs. */
402 Stats::Formula overallMshrMisses;
403
404 /** Number of misses that miss in the MSHRs, per command and thread. */
405 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
406 /** Total number of misses that miss in the MSHRs. */
407 Stats::Formula overallMshrUncacheable;
408
409 /** Total cycle latency of each MSHR miss, per command and thread. */
410 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
411 /** Total cycle latency of demand MSHR misses. */
412 Stats::Formula demandMshrMissLatency;
413 /** Total cycle latency of overall MSHR misses. */
414 Stats::Formula overallMshrMissLatency;
415
416 /** Total cycle latency of each MSHR miss, per command and thread. */
417 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
418 /** Total cycle latency of overall MSHR misses. */
419 Stats::Formula overallMshrUncacheableLatency;
420
421#if 0
422 /** The total number of MSHR accesses per command and thread. */
423 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
424 /** The total number of demand MSHR accesses. */
425 Stats::Formula demandMshrAccesses;
426 /** The total number of MSHR accesses. */
427 Stats::Formula overallMshrAccesses;
428#endif
429
430 /** The miss rate in the MSHRs pre command and thread. */
431 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
432 /** The demand miss rate in the MSHRs. */
433 Stats::Formula demandMshrMissRate;
434 /** The overall miss rate in the MSHRs. */
435 Stats::Formula overallMshrMissRate;
436
437 /** The average latency of an MSHR miss, per command and thread. */
438 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
439 /** The average latency of a demand MSHR miss. */
440 Stats::Formula demandAvgMshrMissLatency;
441 /** The average overall latency of an MSHR miss. */
442 Stats::Formula overallAvgMshrMissLatency;
443
444 /** The average latency of an MSHR miss, per command and thread. */
445 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
446 /** The average overall latency of an MSHR miss. */
447 Stats::Formula overallAvgMshrUncacheableLatency;
448
449 /**
450 * @}
451 */
452
453 /**
454 * Register stats for this object.
455 */
456 virtual void regStats();
457
458 public:
459 BaseCache(const BaseCacheParams *p, unsigned blk_size);
460 ~BaseCache() {}
461
462 virtual void init();
463
464 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
465 PortID idx = InvalidPortID);
466 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
467 PortID idx = InvalidPortID);
468
469 /**
470 * Query block size of a cache.
471 * @return The block size
472 */
473 unsigned
474 getBlockSize() const
475 {
476 return blkSize;
477 }
478
479
480 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
481
482
483 const AddrRangeList &getAddrRanges() const { return addrRanges; }
484
485 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
486 {
487 MSHR *mshr = mshrQueue.allocate(blockAlign(pkt->getAddr()), blkSize,
488 pkt, time, order++,
489 allocOnFill(pkt->cmd));
490
491 if (mshrQueue.isFull()) {
492 setBlocked((BlockedCause)MSHRQueue_MSHRs);
493 }
494
495 if (sched_send) {
496 // schedule the send
497 schedMemSideSendEvent(time);
498 }
499
500 return mshr;
501 }
502
503 void allocateWriteBuffer(PacketPtr pkt, Tick time)
504 {
505 // should only see writes or clean evicts here
506 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
507
508 Addr blk_addr = blockAlign(pkt->getAddr());
509
510 WriteQueueEntry *wq_entry =
511 writeBuffer.findMatch(blk_addr, pkt->isSecure());
512 if (wq_entry && !wq_entry->inService) {
513 DPRINTF(Cache, "Potential to merge writeback %s to %#llx",
514 pkt->cmdString(), pkt->getAddr());
515 }
516
517 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
518
519 if (writeBuffer.isFull()) {
520 setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
521 }
522
523 // schedule the send
524 schedMemSideSendEvent(time);
525 }
526
527 /**
528 * Returns true if the cache is blocked for accesses.
529 */
530 bool isBlocked() const
531 {
532 return blocked != 0;
533 }
534
535 /**
536 * Marks the access path of the cache as blocked for the given cause. This
537 * also sets the blocked flag in the slave interface.
538 * @param cause The reason for the cache blocking.
539 */
540 void setBlocked(BlockedCause cause)
541 {
542 uint8_t flag = 1 << cause;
543 if (blocked == 0) {
544 blocked_causes[cause]++;
545 blockedCycle = curCycle();
546 cpuSidePort->setBlocked();
547 }
548 blocked |= flag;
549 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
550 }
551
552 /**
553 * Marks the cache as unblocked for the given cause. This also clears the
554 * blocked flags in the appropriate interfaces.
555 * @param cause The newly unblocked cause.
556 * @warning Calling this function can cause a blocked request on the bus to
557 * access the cache. The cache must be in a state to handle that request.
558 */
559 void clearBlocked(BlockedCause cause)
560 {
561 uint8_t flag = 1 << cause;
562 blocked &= ~flag;
563 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
564 if (blocked == 0) {
565 blocked_cycles[cause] += curCycle() - blockedCycle;
566 cpuSidePort->clearBlocked();
567 }
568 }
569
570 /**
571 * Schedule a send event for the memory-side port. If already
572 * scheduled, this may reschedule the event at an earlier
573 * time. When the specified time is reached, the port is free to
574 * send either a response, a request, or a prefetch request.
575 *
576 * @param time The time when to attempt sending a packet.
577 */
578 void schedMemSideSendEvent(Tick time)
579 {
580 memSidePort->schedSendEvent(time);
581 }
582
583 virtual bool inCache(Addr addr, bool is_secure) const = 0;
584
585 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
586
587 void incMissCount(PacketPtr pkt)
588 {
589 assert(pkt->req->masterId() < system->maxMasters());
590 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
591 pkt->req->incAccessDepth();
592 if (missCount) {
593 --missCount;
594 if (missCount == 0)
595 exitSimLoop("A cache reached the maximum miss count");
596 }
597 }
598 void incHitCount(PacketPtr pkt)
599 {
600 assert(pkt->req->masterId() < system->maxMasters());
601 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
602
603 }
604
605};
606
607#endif //__MEM_CACHE_BASE_HH__
| 341 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
342 /** Number of misses for demand accesses. */
343 Stats::Formula demandMisses;
344 /** Number of misses for all accesses. */
345 Stats::Formula overallMisses;
346
347 /**
348 * Total number of cycles per thread/command spent waiting for a miss.
349 * Used to calculate the average miss latency.
350 */
351 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
352 /** Total number of cycles spent waiting for demand misses. */
353 Stats::Formula demandMissLatency;
354 /** Total number of cycles spent waiting for all misses. */
355 Stats::Formula overallMissLatency;
356
357 /** The number of accesses per command and thread. */
358 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
359 /** The number of demand accesses. */
360 Stats::Formula demandAccesses;
361 /** The number of overall accesses. */
362 Stats::Formula overallAccesses;
363
364 /** The miss rate per command and thread. */
365 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
366 /** The miss rate of all demand accesses. */
367 Stats::Formula demandMissRate;
368 /** The miss rate for all accesses. */
369 Stats::Formula overallMissRate;
370
371 /** The average miss latency per command and thread. */
372 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
373 /** The average miss latency for demand misses. */
374 Stats::Formula demandAvgMissLatency;
375 /** The average miss latency for all misses. */
376 Stats::Formula overallAvgMissLatency;
377
378 /** The total number of cycles blocked for each blocked cause. */
379 Stats::Vector blocked_cycles;
380 /** The number of times this cache blocked for each blocked cause. */
381 Stats::Vector blocked_causes;
382
383 /** The average number of cycles blocked for each blocked cause. */
384 Stats::Formula avg_blocked;
385
386 /** The number of times a HW-prefetched block is evicted w/o reference. */
387 Stats::Scalar unusedPrefetches;
388
389 /** Number of blocks written back per thread. */
390 Stats::Vector writebacks;
391
392 /** Number of misses that hit in the MSHRs per command and thread. */
393 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
394 /** Demand misses that hit in the MSHRs. */
395 Stats::Formula demandMshrHits;
396 /** Total number of misses that hit in the MSHRs. */
397 Stats::Formula overallMshrHits;
398
399 /** Number of misses that miss in the MSHRs, per command and thread. */
400 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
401 /** Demand misses that miss in the MSHRs. */
402 Stats::Formula demandMshrMisses;
403 /** Total number of misses that miss in the MSHRs. */
404 Stats::Formula overallMshrMisses;
405
406 /** Number of misses that miss in the MSHRs, per command and thread. */
407 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
408 /** Total number of misses that miss in the MSHRs. */
409 Stats::Formula overallMshrUncacheable;
410
411 /** Total cycle latency of each MSHR miss, per command and thread. */
412 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
413 /** Total cycle latency of demand MSHR misses. */
414 Stats::Formula demandMshrMissLatency;
415 /** Total cycle latency of overall MSHR misses. */
416 Stats::Formula overallMshrMissLatency;
417
418 /** Total cycle latency of each MSHR miss, per command and thread. */
419 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
420 /** Total cycle latency of overall MSHR misses. */
421 Stats::Formula overallMshrUncacheableLatency;
422
423#if 0
424 /** The total number of MSHR accesses per command and thread. */
425 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
426 /** The total number of demand MSHR accesses. */
427 Stats::Formula demandMshrAccesses;
428 /** The total number of MSHR accesses. */
429 Stats::Formula overallMshrAccesses;
430#endif
431
432 /** The miss rate in the MSHRs pre command and thread. */
433 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
434 /** The demand miss rate in the MSHRs. */
435 Stats::Formula demandMshrMissRate;
436 /** The overall miss rate in the MSHRs. */
437 Stats::Formula overallMshrMissRate;
438
439 /** The average latency of an MSHR miss, per command and thread. */
440 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
441 /** The average latency of a demand MSHR miss. */
442 Stats::Formula demandAvgMshrMissLatency;
443 /** The average overall latency of an MSHR miss. */
444 Stats::Formula overallAvgMshrMissLatency;
445
446 /** The average latency of an MSHR miss, per command and thread. */
447 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
448 /** The average overall latency of an MSHR miss. */
449 Stats::Formula overallAvgMshrUncacheableLatency;
450
451 /**
452 * @}
453 */
454
455 /**
456 * Register stats for this object.
457 */
458 virtual void regStats();
459
460 public:
461 BaseCache(const BaseCacheParams *p, unsigned blk_size);
462 ~BaseCache() {}
463
464 virtual void init();
465
466 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
467 PortID idx = InvalidPortID);
468 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
469 PortID idx = InvalidPortID);
470
471 /**
472 * Query block size of a cache.
473 * @return The block size
474 */
475 unsigned
476 getBlockSize() const
477 {
478 return blkSize;
479 }
480
481
482 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
483
484
485 const AddrRangeList &getAddrRanges() const { return addrRanges; }
486
487 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool sched_send = true)
488 {
489 MSHR *mshr = mshrQueue.allocate(blockAlign(pkt->getAddr()), blkSize,
490 pkt, time, order++,
491 allocOnFill(pkt->cmd));
492
493 if (mshrQueue.isFull()) {
494 setBlocked((BlockedCause)MSHRQueue_MSHRs);
495 }
496
497 if (sched_send) {
498 // schedule the send
499 schedMemSideSendEvent(time);
500 }
501
502 return mshr;
503 }
504
505 void allocateWriteBuffer(PacketPtr pkt, Tick time)
506 {
507 // should only see writes or clean evicts here
508 assert(pkt->isWrite() || pkt->cmd == MemCmd::CleanEvict);
509
510 Addr blk_addr = blockAlign(pkt->getAddr());
511
512 WriteQueueEntry *wq_entry =
513 writeBuffer.findMatch(blk_addr, pkt->isSecure());
514 if (wq_entry && !wq_entry->inService) {
515 DPRINTF(Cache, "Potential to merge writeback %s to %#llx",
516 pkt->cmdString(), pkt->getAddr());
517 }
518
519 writeBuffer.allocate(blk_addr, blkSize, pkt, time, order++);
520
521 if (writeBuffer.isFull()) {
522 setBlocked((BlockedCause)MSHRQueue_WriteBuffer);
523 }
524
525 // schedule the send
526 schedMemSideSendEvent(time);
527 }
528
529 /**
530 * Returns true if the cache is blocked for accesses.
531 */
532 bool isBlocked() const
533 {
534 return blocked != 0;
535 }
536
537 /**
538 * Marks the access path of the cache as blocked for the given cause. This
539 * also sets the blocked flag in the slave interface.
540 * @param cause The reason for the cache blocking.
541 */
542 void setBlocked(BlockedCause cause)
543 {
544 uint8_t flag = 1 << cause;
545 if (blocked == 0) {
546 blocked_causes[cause]++;
547 blockedCycle = curCycle();
548 cpuSidePort->setBlocked();
549 }
550 blocked |= flag;
551 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
552 }
553
554 /**
555 * Marks the cache as unblocked for the given cause. This also clears the
556 * blocked flags in the appropriate interfaces.
557 * @param cause The newly unblocked cause.
558 * @warning Calling this function can cause a blocked request on the bus to
559 * access the cache. The cache must be in a state to handle that request.
560 */
561 void clearBlocked(BlockedCause cause)
562 {
563 uint8_t flag = 1 << cause;
564 blocked &= ~flag;
565 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
566 if (blocked == 0) {
567 blocked_cycles[cause] += curCycle() - blockedCycle;
568 cpuSidePort->clearBlocked();
569 }
570 }
571
572 /**
573 * Schedule a send event for the memory-side port. If already
574 * scheduled, this may reschedule the event at an earlier
575 * time. When the specified time is reached, the port is free to
576 * send either a response, a request, or a prefetch request.
577 *
578 * @param time The time when to attempt sending a packet.
579 */
580 void schedMemSideSendEvent(Tick time)
581 {
582 memSidePort->schedSendEvent(time);
583 }
584
585 virtual bool inCache(Addr addr, bool is_secure) const = 0;
586
587 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
588
589 void incMissCount(PacketPtr pkt)
590 {
591 assert(pkt->req->masterId() < system->maxMasters());
592 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
593 pkt->req->incAccessDepth();
594 if (missCount) {
595 --missCount;
596 if (missCount == 0)
597 exitSimLoop("A cache reached the maximum miss count");
598 }
599 }
600 void incHitCount(PacketPtr pkt)
601 {
602 assert(pkt->req->masterId() < system->maxMasters());
603 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
604
605 }
606
607};
608
609#endif //__MEM_CACHE_BASE_HH__
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