1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
135 }
136
137 protected:
138
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 MasterPacketQueue &_queue) :
141 QueuedMasterPort(_name, _cache, _queue)
142 { }
143
144 /**
145 * Memory-side port always snoops.
146 *
147 * @return always true
148 */
149 virtual bool isSnooping() const { return true; }
150 };
151
152 /**
153 * A cache slave port is used for the CPU-side port of the cache,
154 * and it is basically a simple timing port that uses a transmit
155 * list for responses to the CPU (or connected master). In
156 * addition, it has the functionality to block the port for
157 * incoming requests. If blocked, the port will issue a retry once
158 * unblocked.
159 */
160 class CacheSlavePort : public QueuedSlavePort
161 {
162
163 public:
164
165 /** Do not accept any new requests. */
166 void setBlocked();
167
168 /** Return to normal operation and accept new requests. */
169 void clearBlocked();
170
171 bool isBlocked() const { return blocked; }
172
173 protected:
174
175 CacheSlavePort(const std::string &_name, BaseCache *_cache,
176 const std::string &_label);
177
178 /** A normal packet queue used to store responses. */
179 SlavePacketQueue queue;
180
181 bool blocked;
182
183 bool mustSendRetry;
184
185 private:
186
187 void processSendRetry();
188
189 EventWrapper<CacheSlavePort,
190 &CacheSlavePort::processSendRetry> sendRetryEvent;
191
192 };
193
194 CacheSlavePort *cpuSidePort;
195 CacheMasterPort *memSidePort;
196
197 protected:
198
199 /** Miss status registers */
200 MSHRQueue mshrQueue;
201
202 /** Write/writeback buffer */
203 MSHRQueue writeBuffer;
204
205 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
206 PacketPtr pkt, Tick time, bool requestBus)
207 {
208 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
209
210 if (mq->isFull()) {
211 setBlocked((BlockedCause)mq->index);
212 }
213
214 if (requestBus) {
215 requestMemSideBus((RequestCause)mq->index, time);
216 }
217
218 return mshr;
219 }
220
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
135 }
136
137 protected:
138
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 MasterPacketQueue &_queue) :
141 QueuedMasterPort(_name, _cache, _queue)
142 { }
143
144 /**
145 * Memory-side port always snoops.
146 *
147 * @return always true
148 */
149 virtual bool isSnooping() const { return true; }
150 };
151
152 /**
153 * A cache slave port is used for the CPU-side port of the cache,
154 * and it is basically a simple timing port that uses a transmit
155 * list for responses to the CPU (or connected master). In
156 * addition, it has the functionality to block the port for
157 * incoming requests. If blocked, the port will issue a retry once
158 * unblocked.
159 */
160 class CacheSlavePort : public QueuedSlavePort
161 {
162
163 public:
164
165 /** Do not accept any new requests. */
166 void setBlocked();
167
168 /** Return to normal operation and accept new requests. */
169 void clearBlocked();
170
171 bool isBlocked() const { return blocked; }
172
173 protected:
174
175 CacheSlavePort(const std::string &_name, BaseCache *_cache,
176 const std::string &_label);
177
178 /** A normal packet queue used to store responses. */
179 SlavePacketQueue queue;
180
181 bool blocked;
182
183 bool mustSendRetry;
184
185 private:
186
187 void processSendRetry();
188
189 EventWrapper<CacheSlavePort,
190 &CacheSlavePort::processSendRetry> sendRetryEvent;
191
192 };
193
194 CacheSlavePort *cpuSidePort;
195 CacheMasterPort *memSidePort;
196
197 protected:
198
199 /** Miss status registers */
200 MSHRQueue mshrQueue;
201
202 /** Write/writeback buffer */
203 MSHRQueue writeBuffer;
204
205 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
206 PacketPtr pkt, Tick time, bool requestBus)
207 {
208 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
209
210 if (mq->isFull()) {
211 setBlocked((BlockedCause)mq->index);
212 }
213
214 if (requestBus) {
215 requestMemSideBus((RequestCause)mq->index, time);
216 }
217
218 return mshr;
219 }
220
|
226 if (wasFull && !mq->isFull()) {
227 clearBlocked((BlockedCause)mq->index);
228 }
229 }
230
231 /**
232 * Write back dirty blocks in the cache using functional accesses.
233 */
234 virtual void memWriteback() = 0;
235 /**
236 * Invalidates all blocks in the cache.
237 *
238 * @warn Dirty cache lines will not be written back to
239 * memory. Make sure to call functionalWriteback() first if you
240 * want the to write them to memory.
241 */
242 virtual void memInvalidate() = 0;
243 /**
244 * Determine if there are any dirty blocks in the cache.
245 *
246 * \return true if at least one block is dirty, false otherwise.
247 */
248 virtual bool isDirty() const = 0;
249
250 /** Block size of this cache */
251 const unsigned blkSize;
252
253 /**
254 * The latency of a hit in this device.
255 */
256 const Cycles hitLatency;
257
258 /**
259 * The latency of sending reponse to its upper level cache/core on a
260 * linefill. In most contemporary processors, the return path on a cache
261 * miss is much quicker that the hit latency. The responseLatency parameter
262 * tries to capture this latency.
263 */
264 const Cycles responseLatency;
265
266 /** The number of targets for each MSHR. */
267 const int numTarget;
268
269 /** Do we forward snoops from mem side port through to cpu side port? */
270 const bool forwardSnoops;
271
272 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
273 * never try to forward ownership and similar optimizations to the cpu
274 * side */
275 const bool isTopLevel;
276
277 /**
278 * Bit vector of the blocking reasons for the access path.
279 * @sa #BlockedCause
280 */
281 uint8_t blocked;
282
283 /** Increasing order number assigned to each incoming request. */
284 uint64_t order;
285
286 /** Stores time the cache blocked for statistics. */
287 Cycles blockedCycle;
288
289 /** Pointer to the MSHR that has no targets. */
290 MSHR *noTargetMSHR;
291
292 /** The number of misses to trigger an exit event. */
293 Counter missCount;
294
295 /**
296 * The address range to which the cache responds on the CPU side.
297 * Normally this is all possible memory addresses. */
298 const AddrRangeList addrRanges;
299
300 public:
301 /** System we are currently operating in. */
302 System *system;
303
304 // Statistics
305 /**
306 * @addtogroup CacheStatistics
307 * @{
308 */
309
310 /** Number of hits per thread for each type of command. @sa Packet::Command */
311 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
312 /** Number of hits for demand accesses. */
313 Stats::Formula demandHits;
314 /** Number of hit for all accesses. */
315 Stats::Formula overallHits;
316
317 /** Number of misses per thread for each type of command. @sa Packet::Command */
318 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
319 /** Number of misses for demand accesses. */
320 Stats::Formula demandMisses;
321 /** Number of misses for all accesses. */
322 Stats::Formula overallMisses;
323
324 /**
325 * Total number of cycles per thread/command spent waiting for a miss.
326 * Used to calculate the average miss latency.
327 */
328 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
329 /** Total number of cycles spent waiting for demand misses. */
330 Stats::Formula demandMissLatency;
331 /** Total number of cycles spent waiting for all misses. */
332 Stats::Formula overallMissLatency;
333
334 /** The number of accesses per command and thread. */
335 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
336 /** The number of demand accesses. */
337 Stats::Formula demandAccesses;
338 /** The number of overall accesses. */
339 Stats::Formula overallAccesses;
340
341 /** The miss rate per command and thread. */
342 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
343 /** The miss rate of all demand accesses. */
344 Stats::Formula demandMissRate;
345 /** The miss rate for all accesses. */
346 Stats::Formula overallMissRate;
347
348 /** The average miss latency per command and thread. */
349 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
350 /** The average miss latency for demand misses. */
351 Stats::Formula demandAvgMissLatency;
352 /** The average miss latency for all misses. */
353 Stats::Formula overallAvgMissLatency;
354
355 /** The total number of cycles blocked for each blocked cause. */
356 Stats::Vector blocked_cycles;
357 /** The number of times this cache blocked for each blocked cause. */
358 Stats::Vector blocked_causes;
359
360 /** The average number of cycles blocked for each blocked cause. */
361 Stats::Formula avg_blocked;
362
363 /** The number of fast writes (WH64) performed. */
364 Stats::Scalar fastWrites;
365
366 /** The number of cache copies performed. */
367 Stats::Scalar cacheCopies;
368
369 /** Number of blocks written back per thread. */
370 Stats::Vector writebacks;
371
372 /** Number of misses that hit in the MSHRs per command and thread. */
373 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
374 /** Demand misses that hit in the MSHRs. */
375 Stats::Formula demandMshrHits;
376 /** Total number of misses that hit in the MSHRs. */
377 Stats::Formula overallMshrHits;
378
379 /** Number of misses that miss in the MSHRs, per command and thread. */
380 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
381 /** Demand misses that miss in the MSHRs. */
382 Stats::Formula demandMshrMisses;
383 /** Total number of misses that miss in the MSHRs. */
384 Stats::Formula overallMshrMisses;
385
386 /** Number of misses that miss in the MSHRs, per command and thread. */
387 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
388 /** Total number of misses that miss in the MSHRs. */
389 Stats::Formula overallMshrUncacheable;
390
391 /** Total cycle latency of each MSHR miss, per command and thread. */
392 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
393 /** Total cycle latency of demand MSHR misses. */
394 Stats::Formula demandMshrMissLatency;
395 /** Total cycle latency of overall MSHR misses. */
396 Stats::Formula overallMshrMissLatency;
397
398 /** Total cycle latency of each MSHR miss, per command and thread. */
399 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
400 /** Total cycle latency of overall MSHR misses. */
401 Stats::Formula overallMshrUncacheableLatency;
402
403#if 0
404 /** The total number of MSHR accesses per command and thread. */
405 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
406 /** The total number of demand MSHR accesses. */
407 Stats::Formula demandMshrAccesses;
408 /** The total number of MSHR accesses. */
409 Stats::Formula overallMshrAccesses;
410#endif
411
412 /** The miss rate in the MSHRs pre command and thread. */
413 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
414 /** The demand miss rate in the MSHRs. */
415 Stats::Formula demandMshrMissRate;
416 /** The overall miss rate in the MSHRs. */
417 Stats::Formula overallMshrMissRate;
418
419 /** The average latency of an MSHR miss, per command and thread. */
420 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
421 /** The average latency of a demand MSHR miss. */
422 Stats::Formula demandAvgMshrMissLatency;
423 /** The average overall latency of an MSHR miss. */
424 Stats::Formula overallAvgMshrMissLatency;
425
426 /** The average latency of an MSHR miss, per command and thread. */
427 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
428 /** The average overall latency of an MSHR miss. */
429 Stats::Formula overallAvgMshrUncacheableLatency;
430
431 /** The number of times a thread hit its MSHR cap. */
432 Stats::Vector mshr_cap_events;
433 /** The number of times software prefetches caused the MSHR to block. */
434 Stats::Vector soft_prefetch_mshr_full;
435
436 Stats::Scalar mshr_no_allocate_misses;
437
438 /**
439 * @}
440 */
441
442 /**
443 * Register stats for this object.
444 */
445 virtual void regStats();
446
447 public:
448 typedef BaseCacheParams Params;
449 BaseCache(const Params *p);
450 ~BaseCache() {}
451
452 virtual void init();
453
454 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
455 PortID idx = InvalidPortID);
456 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
457 PortID idx = InvalidPortID);
458
459 /**
460 * Query block size of a cache.
461 * @return The block size
462 */
463 unsigned
464 getBlockSize() const
465 {
466 return blkSize;
467 }
468
469
470 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
471
472
473 const AddrRangeList &getAddrRanges() const { return addrRanges; }
474
475 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
476 {
477 assert(!pkt->req->isUncacheable());
478 return allocateBufferInternal(&mshrQueue,
479 blockAlign(pkt->getAddr()), blkSize,
480 pkt, time, requestBus);
481 }
482
483 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
484 {
485 assert(pkt->isWrite() && !pkt->isRead());
486 return allocateBufferInternal(&writeBuffer,
487 pkt->getAddr(), pkt->getSize(),
488 pkt, time, requestBus);
489 }
490
491 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
492 {
493 assert(pkt->req->isUncacheable());
494 assert(pkt->isRead());
495 return allocateBufferInternal(&mshrQueue,
496 pkt->getAddr(), pkt->getSize(),
497 pkt, time, requestBus);
498 }
499
500 /**
501 * Returns true if the cache is blocked for accesses.
502 */
503 bool isBlocked() const
504 {
505 return blocked != 0;
506 }
507
508 /**
509 * Marks the access path of the cache as blocked for the given cause. This
510 * also sets the blocked flag in the slave interface.
511 * @param cause The reason for the cache blocking.
512 */
513 void setBlocked(BlockedCause cause)
514 {
515 uint8_t flag = 1 << cause;
516 if (blocked == 0) {
517 blocked_causes[cause]++;
518 blockedCycle = curCycle();
519 cpuSidePort->setBlocked();
520 }
521 blocked |= flag;
522 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
523 }
524
525 /**
526 * Marks the cache as unblocked for the given cause. This also clears the
527 * blocked flags in the appropriate interfaces.
528 * @param cause The newly unblocked cause.
529 * @warning Calling this function can cause a blocked request on the bus to
530 * access the cache. The cache must be in a state to handle that request.
531 */
532 void clearBlocked(BlockedCause cause)
533 {
534 uint8_t flag = 1 << cause;
535 blocked &= ~flag;
536 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
537 if (blocked == 0) {
538 blocked_cycles[cause] += curCycle() - blockedCycle;
539 cpuSidePort->clearBlocked();
540 }
541 }
542
543 /**
544 * Request the master bus for the given cause and time.
545 * @param cause The reason for the request.
546 * @param time The time to make the request.
547 */
548 void requestMemSideBus(RequestCause cause, Tick time)
549 {
550 memSidePort->requestBus(cause, time);
551 }
552
553 /**
554 * Clear the master bus request for the given cause.
555 * @param cause The request reason to clear.
556 */
557 void deassertMemSideBusRequest(RequestCause cause)
558 {
559 // Obsolete... we no longer signal bus requests explicitly so
560 // we can't deassert them. Leaving this in as a no-op since
561 // the prefetcher calls it to indicate that it no longer wants
562 // to request a prefetch, and someday that might be
563 // interesting again.
564 }
565
566 virtual unsigned int drain(DrainManager *dm);
567
568 virtual bool inCache(Addr addr, bool is_secure) const = 0;
569
570 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
571
572 void incMissCount(PacketPtr pkt)
573 {
574 assert(pkt->req->masterId() < system->maxMasters());
575 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
576 pkt->req->incAccessDepth();
577 if (missCount) {
578 --missCount;
579 if (missCount == 0)
580 exitSimLoop("A cache reached the maximum miss count");
581 }
582 }
583 void incHitCount(PacketPtr pkt)
584 {
585 assert(pkt->req->masterId() < system->maxMasters());
586 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
587
588 }
589
590};
591
592#endif //__BASE_CACHE_HH__
| 226 if (wasFull && !mq->isFull()) {
227 clearBlocked((BlockedCause)mq->index);
228 }
229 }
230
231 /**
232 * Write back dirty blocks in the cache using functional accesses.
233 */
234 virtual void memWriteback() = 0;
235 /**
236 * Invalidates all blocks in the cache.
237 *
238 * @warn Dirty cache lines will not be written back to
239 * memory. Make sure to call functionalWriteback() first if you
240 * want the to write them to memory.
241 */
242 virtual void memInvalidate() = 0;
243 /**
244 * Determine if there are any dirty blocks in the cache.
245 *
246 * \return true if at least one block is dirty, false otherwise.
247 */
248 virtual bool isDirty() const = 0;
249
250 /** Block size of this cache */
251 const unsigned blkSize;
252
253 /**
254 * The latency of a hit in this device.
255 */
256 const Cycles hitLatency;
257
258 /**
259 * The latency of sending reponse to its upper level cache/core on a
260 * linefill. In most contemporary processors, the return path on a cache
261 * miss is much quicker that the hit latency. The responseLatency parameter
262 * tries to capture this latency.
263 */
264 const Cycles responseLatency;
265
266 /** The number of targets for each MSHR. */
267 const int numTarget;
268
269 /** Do we forward snoops from mem side port through to cpu side port? */
270 const bool forwardSnoops;
271
272 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
273 * never try to forward ownership and similar optimizations to the cpu
274 * side */
275 const bool isTopLevel;
276
277 /**
278 * Bit vector of the blocking reasons for the access path.
279 * @sa #BlockedCause
280 */
281 uint8_t blocked;
282
283 /** Increasing order number assigned to each incoming request. */
284 uint64_t order;
285
286 /** Stores time the cache blocked for statistics. */
287 Cycles blockedCycle;
288
289 /** Pointer to the MSHR that has no targets. */
290 MSHR *noTargetMSHR;
291
292 /** The number of misses to trigger an exit event. */
293 Counter missCount;
294
295 /**
296 * The address range to which the cache responds on the CPU side.
297 * Normally this is all possible memory addresses. */
298 const AddrRangeList addrRanges;
299
300 public:
301 /** System we are currently operating in. */
302 System *system;
303
304 // Statistics
305 /**
306 * @addtogroup CacheStatistics
307 * @{
308 */
309
310 /** Number of hits per thread for each type of command. @sa Packet::Command */
311 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
312 /** Number of hits for demand accesses. */
313 Stats::Formula demandHits;
314 /** Number of hit for all accesses. */
315 Stats::Formula overallHits;
316
317 /** Number of misses per thread for each type of command. @sa Packet::Command */
318 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
319 /** Number of misses for demand accesses. */
320 Stats::Formula demandMisses;
321 /** Number of misses for all accesses. */
322 Stats::Formula overallMisses;
323
324 /**
325 * Total number of cycles per thread/command spent waiting for a miss.
326 * Used to calculate the average miss latency.
327 */
328 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
329 /** Total number of cycles spent waiting for demand misses. */
330 Stats::Formula demandMissLatency;
331 /** Total number of cycles spent waiting for all misses. */
332 Stats::Formula overallMissLatency;
333
334 /** The number of accesses per command and thread. */
335 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
336 /** The number of demand accesses. */
337 Stats::Formula demandAccesses;
338 /** The number of overall accesses. */
339 Stats::Formula overallAccesses;
340
341 /** The miss rate per command and thread. */
342 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
343 /** The miss rate of all demand accesses. */
344 Stats::Formula demandMissRate;
345 /** The miss rate for all accesses. */
346 Stats::Formula overallMissRate;
347
348 /** The average miss latency per command and thread. */
349 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
350 /** The average miss latency for demand misses. */
351 Stats::Formula demandAvgMissLatency;
352 /** The average miss latency for all misses. */
353 Stats::Formula overallAvgMissLatency;
354
355 /** The total number of cycles blocked for each blocked cause. */
356 Stats::Vector blocked_cycles;
357 /** The number of times this cache blocked for each blocked cause. */
358 Stats::Vector blocked_causes;
359
360 /** The average number of cycles blocked for each blocked cause. */
361 Stats::Formula avg_blocked;
362
363 /** The number of fast writes (WH64) performed. */
364 Stats::Scalar fastWrites;
365
366 /** The number of cache copies performed. */
367 Stats::Scalar cacheCopies;
368
369 /** Number of blocks written back per thread. */
370 Stats::Vector writebacks;
371
372 /** Number of misses that hit in the MSHRs per command and thread. */
373 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
374 /** Demand misses that hit in the MSHRs. */
375 Stats::Formula demandMshrHits;
376 /** Total number of misses that hit in the MSHRs. */
377 Stats::Formula overallMshrHits;
378
379 /** Number of misses that miss in the MSHRs, per command and thread. */
380 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
381 /** Demand misses that miss in the MSHRs. */
382 Stats::Formula demandMshrMisses;
383 /** Total number of misses that miss in the MSHRs. */
384 Stats::Formula overallMshrMisses;
385
386 /** Number of misses that miss in the MSHRs, per command and thread. */
387 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
388 /** Total number of misses that miss in the MSHRs. */
389 Stats::Formula overallMshrUncacheable;
390
391 /** Total cycle latency of each MSHR miss, per command and thread. */
392 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
393 /** Total cycle latency of demand MSHR misses. */
394 Stats::Formula demandMshrMissLatency;
395 /** Total cycle latency of overall MSHR misses. */
396 Stats::Formula overallMshrMissLatency;
397
398 /** Total cycle latency of each MSHR miss, per command and thread. */
399 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
400 /** Total cycle latency of overall MSHR misses. */
401 Stats::Formula overallMshrUncacheableLatency;
402
403#if 0
404 /** The total number of MSHR accesses per command and thread. */
405 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
406 /** The total number of demand MSHR accesses. */
407 Stats::Formula demandMshrAccesses;
408 /** The total number of MSHR accesses. */
409 Stats::Formula overallMshrAccesses;
410#endif
411
412 /** The miss rate in the MSHRs pre command and thread. */
413 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
414 /** The demand miss rate in the MSHRs. */
415 Stats::Formula demandMshrMissRate;
416 /** The overall miss rate in the MSHRs. */
417 Stats::Formula overallMshrMissRate;
418
419 /** The average latency of an MSHR miss, per command and thread. */
420 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
421 /** The average latency of a demand MSHR miss. */
422 Stats::Formula demandAvgMshrMissLatency;
423 /** The average overall latency of an MSHR miss. */
424 Stats::Formula overallAvgMshrMissLatency;
425
426 /** The average latency of an MSHR miss, per command and thread. */
427 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
428 /** The average overall latency of an MSHR miss. */
429 Stats::Formula overallAvgMshrUncacheableLatency;
430
431 /** The number of times a thread hit its MSHR cap. */
432 Stats::Vector mshr_cap_events;
433 /** The number of times software prefetches caused the MSHR to block. */
434 Stats::Vector soft_prefetch_mshr_full;
435
436 Stats::Scalar mshr_no_allocate_misses;
437
438 /**
439 * @}
440 */
441
442 /**
443 * Register stats for this object.
444 */
445 virtual void regStats();
446
447 public:
448 typedef BaseCacheParams Params;
449 BaseCache(const Params *p);
450 ~BaseCache() {}
451
452 virtual void init();
453
454 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
455 PortID idx = InvalidPortID);
456 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
457 PortID idx = InvalidPortID);
458
459 /**
460 * Query block size of a cache.
461 * @return The block size
462 */
463 unsigned
464 getBlockSize() const
465 {
466 return blkSize;
467 }
468
469
470 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
471
472
473 const AddrRangeList &getAddrRanges() const { return addrRanges; }
474
475 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
476 {
477 assert(!pkt->req->isUncacheable());
478 return allocateBufferInternal(&mshrQueue,
479 blockAlign(pkt->getAddr()), blkSize,
480 pkt, time, requestBus);
481 }
482
483 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
484 {
485 assert(pkt->isWrite() && !pkt->isRead());
486 return allocateBufferInternal(&writeBuffer,
487 pkt->getAddr(), pkt->getSize(),
488 pkt, time, requestBus);
489 }
490
491 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
492 {
493 assert(pkt->req->isUncacheable());
494 assert(pkt->isRead());
495 return allocateBufferInternal(&mshrQueue,
496 pkt->getAddr(), pkt->getSize(),
497 pkt, time, requestBus);
498 }
499
500 /**
501 * Returns true if the cache is blocked for accesses.
502 */
503 bool isBlocked() const
504 {
505 return blocked != 0;
506 }
507
508 /**
509 * Marks the access path of the cache as blocked for the given cause. This
510 * also sets the blocked flag in the slave interface.
511 * @param cause The reason for the cache blocking.
512 */
513 void setBlocked(BlockedCause cause)
514 {
515 uint8_t flag = 1 << cause;
516 if (blocked == 0) {
517 blocked_causes[cause]++;
518 blockedCycle = curCycle();
519 cpuSidePort->setBlocked();
520 }
521 blocked |= flag;
522 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
523 }
524
525 /**
526 * Marks the cache as unblocked for the given cause. This also clears the
527 * blocked flags in the appropriate interfaces.
528 * @param cause The newly unblocked cause.
529 * @warning Calling this function can cause a blocked request on the bus to
530 * access the cache. The cache must be in a state to handle that request.
531 */
532 void clearBlocked(BlockedCause cause)
533 {
534 uint8_t flag = 1 << cause;
535 blocked &= ~flag;
536 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
537 if (blocked == 0) {
538 blocked_cycles[cause] += curCycle() - blockedCycle;
539 cpuSidePort->clearBlocked();
540 }
541 }
542
543 /**
544 * Request the master bus for the given cause and time.
545 * @param cause The reason for the request.
546 * @param time The time to make the request.
547 */
548 void requestMemSideBus(RequestCause cause, Tick time)
549 {
550 memSidePort->requestBus(cause, time);
551 }
552
553 /**
554 * Clear the master bus request for the given cause.
555 * @param cause The request reason to clear.
556 */
557 void deassertMemSideBusRequest(RequestCause cause)
558 {
559 // Obsolete... we no longer signal bus requests explicitly so
560 // we can't deassert them. Leaving this in as a no-op since
561 // the prefetcher calls it to indicate that it no longer wants
562 // to request a prefetch, and someday that might be
563 // interesting again.
564 }
565
566 virtual unsigned int drain(DrainManager *dm);
567
568 virtual bool inCache(Addr addr, bool is_secure) const = 0;
569
570 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
571
572 void incMissCount(PacketPtr pkt)
573 {
574 assert(pkt->req->masterId() < system->maxMasters());
575 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
576 pkt->req->incAccessDepth();
577 if (missCount) {
578 --missCount;
579 if (missCount == 0)
580 exitSimLoop("A cache reached the maximum miss count");
581 }
582 }
583 void incHitCount(PacketPtr pkt)
584 {
585 assert(pkt->req->masterId() < system->maxMasters());
586 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
587
588 }
589
590};
591
592#endif //__BASE_CACHE_HH__
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