1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
|
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
135 }
136
137 protected:
138
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 MasterPacketQueue &_queue) :
141 QueuedMasterPort(_name, _cache, _queue)
142 { }
143
144 /**
145 * Memory-side port always snoops.
146 *
147 * @return always true
148 */
149 virtual bool isSnooping() const { return true; }
150 };
151
152 /**
153 * A cache slave port is used for the CPU-side port of the cache,
154 * and it is basically a simple timing port that uses a transmit
155 * list for responses to the CPU (or connected master). In
156 * addition, it has the functionality to block the port for
157 * incoming requests. If blocked, the port will issue a retry once
158 * unblocked.
159 */
160 class CacheSlavePort : public QueuedSlavePort
161 {
162
163 public:
164
165 /** Do not accept any new requests. */
166 void setBlocked();
167
168 /** Return to normal operation and accept new requests. */
169 void clearBlocked();
170
| 98 NUM_BLOCKED_CAUSES
99 };
100
101 /**
102 * Reasons for cache to request a bus.
103 */
104 enum RequestCause {
105 Request_MSHR = MSHRQueue_MSHRs,
106 Request_WB = MSHRQueue_WriteBuffer,
107 Request_PF,
108 NUM_REQUEST_CAUSES
109 };
110
111 protected:
112
113 /**
114 * A cache master port is used for the memory-side port of the
115 * cache, and in addition to the basic timing port that only sends
116 * response packets through a transmit list, it also offers the
117 * ability to schedule and send request packets (requests &
118 * writebacks). The send event is scheduled through requestBus,
119 * and the sendDeferredPacket of the timing port is modified to
120 * consider both the transmit list and the requests from the MSHR.
121 */
122 class CacheMasterPort : public QueuedMasterPort
123 {
124
125 public:
126
127 /**
128 * Schedule a send of a request packet (from the MSHR). Note
129 * that we could already have a retry or a transmit list of
130 * responses outstanding.
131 */
132 void requestBus(RequestCause cause, Tick time)
133 {
134 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
135 queue.schedSendEvent(time);
136 }
137
138 protected:
139
140 CacheMasterPort(const std::string &_name, BaseCache *_cache,
141 MasterPacketQueue &_queue) :
142 QueuedMasterPort(_name, _cache, _queue)
143 { }
144
145 /**
146 * Memory-side port always snoops.
147 *
148 * @return always true
149 */
150 virtual bool isSnooping() const { return true; }
151 };
152
153 /**
154 * A cache slave port is used for the CPU-side port of the cache,
155 * and it is basically a simple timing port that uses a transmit
156 * list for responses to the CPU (or connected master). In
157 * addition, it has the functionality to block the port for
158 * incoming requests. If blocked, the port will issue a retry once
159 * unblocked.
160 */
161 class CacheSlavePort : public QueuedSlavePort
162 {
163
164 public:
165
166 /** Do not accept any new requests. */
167 void setBlocked();
168
169 /** Return to normal operation and accept new requests. */
170 void clearBlocked();
171
|
171 protected:
172
173 CacheSlavePort(const std::string &_name, BaseCache *_cache,
174 const std::string &_label);
175
176 /** A normal packet queue used to store responses. */
177 SlavePacketQueue queue;
178
179 bool blocked;
180
181 bool mustSendRetry;
182
183 private:
184
185 void processSendRetry();
186
187 EventWrapper<CacheSlavePort,
188 &CacheSlavePort::processSendRetry> sendRetryEvent;
189
190 };
191
192 CacheSlavePort *cpuSidePort;
193 CacheMasterPort *memSidePort;
194
195 protected:
196
197 /** Miss status registers */
198 MSHRQueue mshrQueue;
199
200 /** Write/writeback buffer */
201 MSHRQueue writeBuffer;
202
203 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
204 PacketPtr pkt, Tick time, bool requestBus)
205 {
206 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
207
208 if (mq->isFull()) {
209 setBlocked((BlockedCause)mq->index);
210 }
211
212 if (requestBus) {
213 requestMemSideBus((RequestCause)mq->index, time);
214 }
215
216 return mshr;
217 }
218
219 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
220 {
221 MSHRQueue *mq = mshr->queue;
222 bool wasFull = mq->isFull();
223 mq->markInService(mshr, pkt);
224 if (wasFull && !mq->isFull()) {
225 clearBlocked((BlockedCause)mq->index);
226 }
227 }
228
229 /**
230 * Write back dirty blocks in the cache using functional accesses.
231 */
232 virtual void memWriteback() = 0;
233 /**
234 * Invalidates all blocks in the cache.
235 *
236 * @warn Dirty cache lines will not be written back to
237 * memory. Make sure to call functionalWriteback() first if you
238 * want the to write them to memory.
239 */
240 virtual void memInvalidate() = 0;
241 /**
242 * Determine if there are any dirty blocks in the cache.
243 *
244 * \return true if at least one block is dirty, false otherwise.
245 */
246 virtual bool isDirty() const = 0;
247
248 /** Block size of this cache */
249 const unsigned blkSize;
250
251 /**
252 * The latency of a hit in this device.
253 */
254 const Cycles hitLatency;
255
256 /**
257 * The latency of sending reponse to its upper level cache/core on a
258 * linefill. In most contemporary processors, the return path on a cache
259 * miss is much quicker that the hit latency. The responseLatency parameter
260 * tries to capture this latency.
261 */
262 const Cycles responseLatency;
263
264 /** The number of targets for each MSHR. */
265 const int numTarget;
266
267 /** Do we forward snoops from mem side port through to cpu side port? */
268 const bool forwardSnoops;
269
270 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
271 * never try to forward ownership and similar optimizations to the cpu
272 * side */
273 const bool isTopLevel;
274
275 /**
276 * Bit vector of the blocking reasons for the access path.
277 * @sa #BlockedCause
278 */
279 uint8_t blocked;
280
281 /** Increasing order number assigned to each incoming request. */
282 uint64_t order;
283
284 /** Stores time the cache blocked for statistics. */
285 Cycles blockedCycle;
286
287 /** Pointer to the MSHR that has no targets. */
288 MSHR *noTargetMSHR;
289
290 /** The number of misses to trigger an exit event. */
291 Counter missCount;
292
293 /**
294 * The address range to which the cache responds on the CPU side.
295 * Normally this is all possible memory addresses. */
296 const AddrRangeList addrRanges;
297
298 public:
299 /** System we are currently operating in. */
300 System *system;
301
302 // Statistics
303 /**
304 * @addtogroup CacheStatistics
305 * @{
306 */
307
308 /** Number of hits per thread for each type of command. @sa Packet::Command */
309 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
310 /** Number of hits for demand accesses. */
311 Stats::Formula demandHits;
312 /** Number of hit for all accesses. */
313 Stats::Formula overallHits;
314
315 /** Number of misses per thread for each type of command. @sa Packet::Command */
316 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
317 /** Number of misses for demand accesses. */
318 Stats::Formula demandMisses;
319 /** Number of misses for all accesses. */
320 Stats::Formula overallMisses;
321
322 /**
323 * Total number of cycles per thread/command spent waiting for a miss.
324 * Used to calculate the average miss latency.
325 */
326 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
327 /** Total number of cycles spent waiting for demand misses. */
328 Stats::Formula demandMissLatency;
329 /** Total number of cycles spent waiting for all misses. */
330 Stats::Formula overallMissLatency;
331
332 /** The number of accesses per command and thread. */
333 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
334 /** The number of demand accesses. */
335 Stats::Formula demandAccesses;
336 /** The number of overall accesses. */
337 Stats::Formula overallAccesses;
338
339 /** The miss rate per command and thread. */
340 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
341 /** The miss rate of all demand accesses. */
342 Stats::Formula demandMissRate;
343 /** The miss rate for all accesses. */
344 Stats::Formula overallMissRate;
345
346 /** The average miss latency per command and thread. */
347 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
348 /** The average miss latency for demand misses. */
349 Stats::Formula demandAvgMissLatency;
350 /** The average miss latency for all misses. */
351 Stats::Formula overallAvgMissLatency;
352
353 /** The total number of cycles blocked for each blocked cause. */
354 Stats::Vector blocked_cycles;
355 /** The number of times this cache blocked for each blocked cause. */
356 Stats::Vector blocked_causes;
357
358 /** The average number of cycles blocked for each blocked cause. */
359 Stats::Formula avg_blocked;
360
361 /** The number of fast writes (WH64) performed. */
362 Stats::Scalar fastWrites;
363
364 /** The number of cache copies performed. */
365 Stats::Scalar cacheCopies;
366
367 /** Number of blocks written back per thread. */
368 Stats::Vector writebacks;
369
370 /** Number of misses that hit in the MSHRs per command and thread. */
371 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
372 /** Demand misses that hit in the MSHRs. */
373 Stats::Formula demandMshrHits;
374 /** Total number of misses that hit in the MSHRs. */
375 Stats::Formula overallMshrHits;
376
377 /** Number of misses that miss in the MSHRs, per command and thread. */
378 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
379 /** Demand misses that miss in the MSHRs. */
380 Stats::Formula demandMshrMisses;
381 /** Total number of misses that miss in the MSHRs. */
382 Stats::Formula overallMshrMisses;
383
384 /** Number of misses that miss in the MSHRs, per command and thread. */
385 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
386 /** Total number of misses that miss in the MSHRs. */
387 Stats::Formula overallMshrUncacheable;
388
389 /** Total cycle latency of each MSHR miss, per command and thread. */
390 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
391 /** Total cycle latency of demand MSHR misses. */
392 Stats::Formula demandMshrMissLatency;
393 /** Total cycle latency of overall MSHR misses. */
394 Stats::Formula overallMshrMissLatency;
395
396 /** Total cycle latency of each MSHR miss, per command and thread. */
397 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
398 /** Total cycle latency of overall MSHR misses. */
399 Stats::Formula overallMshrUncacheableLatency;
400
401#if 0
402 /** The total number of MSHR accesses per command and thread. */
403 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
404 /** The total number of demand MSHR accesses. */
405 Stats::Formula demandMshrAccesses;
406 /** The total number of MSHR accesses. */
407 Stats::Formula overallMshrAccesses;
408#endif
409
410 /** The miss rate in the MSHRs pre command and thread. */
411 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
412 /** The demand miss rate in the MSHRs. */
413 Stats::Formula demandMshrMissRate;
414 /** The overall miss rate in the MSHRs. */
415 Stats::Formula overallMshrMissRate;
416
417 /** The average latency of an MSHR miss, per command and thread. */
418 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
419 /** The average latency of a demand MSHR miss. */
420 Stats::Formula demandAvgMshrMissLatency;
421 /** The average overall latency of an MSHR miss. */
422 Stats::Formula overallAvgMshrMissLatency;
423
424 /** The average latency of an MSHR miss, per command and thread. */
425 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
426 /** The average overall latency of an MSHR miss. */
427 Stats::Formula overallAvgMshrUncacheableLatency;
428
429 /** The number of times a thread hit its MSHR cap. */
430 Stats::Vector mshr_cap_events;
431 /** The number of times software prefetches caused the MSHR to block. */
432 Stats::Vector soft_prefetch_mshr_full;
433
434 Stats::Scalar mshr_no_allocate_misses;
435
436 /**
437 * @}
438 */
439
440 /**
441 * Register stats for this object.
442 */
443 virtual void regStats();
444
445 public:
446 typedef BaseCacheParams Params;
447 BaseCache(const Params *p);
448 ~BaseCache() {}
449
450 virtual void init();
451
452 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
453 PortID idx = InvalidPortID);
454 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
455 PortID idx = InvalidPortID);
456
457 /**
458 * Query block size of a cache.
459 * @return The block size
460 */
461 unsigned
462 getBlockSize() const
463 {
464 return blkSize;
465 }
466
467
468 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
469
470
471 const AddrRangeList &getAddrRanges() const { return addrRanges; }
472
473 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
474 {
475 assert(!pkt->req->isUncacheable());
476 return allocateBufferInternal(&mshrQueue,
477 blockAlign(pkt->getAddr()), blkSize,
478 pkt, time, requestBus);
479 }
480
481 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
482 {
483 assert(pkt->isWrite() && !pkt->isRead());
484 return allocateBufferInternal(&writeBuffer,
485 pkt->getAddr(), pkt->getSize(),
486 pkt, time, requestBus);
487 }
488
489 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
490 {
491 assert(pkt->req->isUncacheable());
492 assert(pkt->isRead());
493 return allocateBufferInternal(&mshrQueue,
494 pkt->getAddr(), pkt->getSize(),
495 pkt, time, requestBus);
496 }
497
498 /**
499 * Returns true if the cache is blocked for accesses.
500 */
501 bool isBlocked() const
502 {
503 return blocked != 0;
504 }
505
506 /**
507 * Marks the access path of the cache as blocked for the given cause. This
508 * also sets the blocked flag in the slave interface.
509 * @param cause The reason for the cache blocking.
510 */
511 void setBlocked(BlockedCause cause)
512 {
513 uint8_t flag = 1 << cause;
514 if (blocked == 0) {
515 blocked_causes[cause]++;
516 blockedCycle = curCycle();
517 cpuSidePort->setBlocked();
518 }
519 blocked |= flag;
520 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
521 }
522
523 /**
524 * Marks the cache as unblocked for the given cause. This also clears the
525 * blocked flags in the appropriate interfaces.
526 * @param cause The newly unblocked cause.
527 * @warning Calling this function can cause a blocked request on the bus to
528 * access the cache. The cache must be in a state to handle that request.
529 */
530 void clearBlocked(BlockedCause cause)
531 {
532 uint8_t flag = 1 << cause;
533 blocked &= ~flag;
534 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
535 if (blocked == 0) {
536 blocked_cycles[cause] += curCycle() - blockedCycle;
537 cpuSidePort->clearBlocked();
538 }
539 }
540
541 /**
542 * Request the master bus for the given cause and time.
543 * @param cause The reason for the request.
544 * @param time The time to make the request.
545 */
546 void requestMemSideBus(RequestCause cause, Tick time)
547 {
548 memSidePort->requestBus(cause, time);
549 }
550
551 /**
552 * Clear the master bus request for the given cause.
553 * @param cause The request reason to clear.
554 */
555 void deassertMemSideBusRequest(RequestCause cause)
556 {
557 // Obsolete... we no longer signal bus requests explicitly so
558 // we can't deassert them. Leaving this in as a no-op since
559 // the prefetcher calls it to indicate that it no longer wants
560 // to request a prefetch, and someday that might be
561 // interesting again.
562 }
563
564 virtual unsigned int drain(DrainManager *dm);
565
566 virtual bool inCache(Addr addr, bool is_secure) const = 0;
567
568 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
569
570 void incMissCount(PacketPtr pkt)
571 {
572 assert(pkt->req->masterId() < system->maxMasters());
573 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
574 pkt->req->incAccessDepth();
575 if (missCount) {
576 --missCount;
577 if (missCount == 0)
578 exitSimLoop("A cache reached the maximum miss count");
579 }
580 }
581 void incHitCount(PacketPtr pkt)
582 {
583 assert(pkt->req->masterId() < system->maxMasters());
584 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
585
586 }
587
588};
589
590#endif //__BASE_CACHE_HH__
| 174 protected:
175
176 CacheSlavePort(const std::string &_name, BaseCache *_cache,
177 const std::string &_label);
178
179 /** A normal packet queue used to store responses. */
180 SlavePacketQueue queue;
181
182 bool blocked;
183
184 bool mustSendRetry;
185
186 private:
187
188 void processSendRetry();
189
190 EventWrapper<CacheSlavePort,
191 &CacheSlavePort::processSendRetry> sendRetryEvent;
192
193 };
194
195 CacheSlavePort *cpuSidePort;
196 CacheMasterPort *memSidePort;
197
198 protected:
199
200 /** Miss status registers */
201 MSHRQueue mshrQueue;
202
203 /** Write/writeback buffer */
204 MSHRQueue writeBuffer;
205
206 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
207 PacketPtr pkt, Tick time, bool requestBus)
208 {
209 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
210
211 if (mq->isFull()) {
212 setBlocked((BlockedCause)mq->index);
213 }
214
215 if (requestBus) {
216 requestMemSideBus((RequestCause)mq->index, time);
217 }
218
219 return mshr;
220 }
221
222 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
223 {
224 MSHRQueue *mq = mshr->queue;
225 bool wasFull = mq->isFull();
226 mq->markInService(mshr, pkt);
227 if (wasFull && !mq->isFull()) {
228 clearBlocked((BlockedCause)mq->index);
229 }
230 }
231
232 /**
233 * Write back dirty blocks in the cache using functional accesses.
234 */
235 virtual void memWriteback() = 0;
236 /**
237 * Invalidates all blocks in the cache.
238 *
239 * @warn Dirty cache lines will not be written back to
240 * memory. Make sure to call functionalWriteback() first if you
241 * want the to write them to memory.
242 */
243 virtual void memInvalidate() = 0;
244 /**
245 * Determine if there are any dirty blocks in the cache.
246 *
247 * \return true if at least one block is dirty, false otherwise.
248 */
249 virtual bool isDirty() const = 0;
250
251 /** Block size of this cache */
252 const unsigned blkSize;
253
254 /**
255 * The latency of a hit in this device.
256 */
257 const Cycles hitLatency;
258
259 /**
260 * The latency of sending reponse to its upper level cache/core on a
261 * linefill. In most contemporary processors, the return path on a cache
262 * miss is much quicker that the hit latency. The responseLatency parameter
263 * tries to capture this latency.
264 */
265 const Cycles responseLatency;
266
267 /** The number of targets for each MSHR. */
268 const int numTarget;
269
270 /** Do we forward snoops from mem side port through to cpu side port? */
271 const bool forwardSnoops;
272
273 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
274 * never try to forward ownership and similar optimizations to the cpu
275 * side */
276 const bool isTopLevel;
277
278 /**
279 * Bit vector of the blocking reasons for the access path.
280 * @sa #BlockedCause
281 */
282 uint8_t blocked;
283
284 /** Increasing order number assigned to each incoming request. */
285 uint64_t order;
286
287 /** Stores time the cache blocked for statistics. */
288 Cycles blockedCycle;
289
290 /** Pointer to the MSHR that has no targets. */
291 MSHR *noTargetMSHR;
292
293 /** The number of misses to trigger an exit event. */
294 Counter missCount;
295
296 /**
297 * The address range to which the cache responds on the CPU side.
298 * Normally this is all possible memory addresses. */
299 const AddrRangeList addrRanges;
300
301 public:
302 /** System we are currently operating in. */
303 System *system;
304
305 // Statistics
306 /**
307 * @addtogroup CacheStatistics
308 * @{
309 */
310
311 /** Number of hits per thread for each type of command. @sa Packet::Command */
312 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
313 /** Number of hits for demand accesses. */
314 Stats::Formula demandHits;
315 /** Number of hit for all accesses. */
316 Stats::Formula overallHits;
317
318 /** Number of misses per thread for each type of command. @sa Packet::Command */
319 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
320 /** Number of misses for demand accesses. */
321 Stats::Formula demandMisses;
322 /** Number of misses for all accesses. */
323 Stats::Formula overallMisses;
324
325 /**
326 * Total number of cycles per thread/command spent waiting for a miss.
327 * Used to calculate the average miss latency.
328 */
329 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
330 /** Total number of cycles spent waiting for demand misses. */
331 Stats::Formula demandMissLatency;
332 /** Total number of cycles spent waiting for all misses. */
333 Stats::Formula overallMissLatency;
334
335 /** The number of accesses per command and thread. */
336 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
337 /** The number of demand accesses. */
338 Stats::Formula demandAccesses;
339 /** The number of overall accesses. */
340 Stats::Formula overallAccesses;
341
342 /** The miss rate per command and thread. */
343 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
344 /** The miss rate of all demand accesses. */
345 Stats::Formula demandMissRate;
346 /** The miss rate for all accesses. */
347 Stats::Formula overallMissRate;
348
349 /** The average miss latency per command and thread. */
350 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
351 /** The average miss latency for demand misses. */
352 Stats::Formula demandAvgMissLatency;
353 /** The average miss latency for all misses. */
354 Stats::Formula overallAvgMissLatency;
355
356 /** The total number of cycles blocked for each blocked cause. */
357 Stats::Vector blocked_cycles;
358 /** The number of times this cache blocked for each blocked cause. */
359 Stats::Vector blocked_causes;
360
361 /** The average number of cycles blocked for each blocked cause. */
362 Stats::Formula avg_blocked;
363
364 /** The number of fast writes (WH64) performed. */
365 Stats::Scalar fastWrites;
366
367 /** The number of cache copies performed. */
368 Stats::Scalar cacheCopies;
369
370 /** Number of blocks written back per thread. */
371 Stats::Vector writebacks;
372
373 /** Number of misses that hit in the MSHRs per command and thread. */
374 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
375 /** Demand misses that hit in the MSHRs. */
376 Stats::Formula demandMshrHits;
377 /** Total number of misses that hit in the MSHRs. */
378 Stats::Formula overallMshrHits;
379
380 /** Number of misses that miss in the MSHRs, per command and thread. */
381 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
382 /** Demand misses that miss in the MSHRs. */
383 Stats::Formula demandMshrMisses;
384 /** Total number of misses that miss in the MSHRs. */
385 Stats::Formula overallMshrMisses;
386
387 /** Number of misses that miss in the MSHRs, per command and thread. */
388 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
389 /** Total number of misses that miss in the MSHRs. */
390 Stats::Formula overallMshrUncacheable;
391
392 /** Total cycle latency of each MSHR miss, per command and thread. */
393 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
394 /** Total cycle latency of demand MSHR misses. */
395 Stats::Formula demandMshrMissLatency;
396 /** Total cycle latency of overall MSHR misses. */
397 Stats::Formula overallMshrMissLatency;
398
399 /** Total cycle latency of each MSHR miss, per command and thread. */
400 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
401 /** Total cycle latency of overall MSHR misses. */
402 Stats::Formula overallMshrUncacheableLatency;
403
404#if 0
405 /** The total number of MSHR accesses per command and thread. */
406 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
407 /** The total number of demand MSHR accesses. */
408 Stats::Formula demandMshrAccesses;
409 /** The total number of MSHR accesses. */
410 Stats::Formula overallMshrAccesses;
411#endif
412
413 /** The miss rate in the MSHRs pre command and thread. */
414 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
415 /** The demand miss rate in the MSHRs. */
416 Stats::Formula demandMshrMissRate;
417 /** The overall miss rate in the MSHRs. */
418 Stats::Formula overallMshrMissRate;
419
420 /** The average latency of an MSHR miss, per command and thread. */
421 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
422 /** The average latency of a demand MSHR miss. */
423 Stats::Formula demandAvgMshrMissLatency;
424 /** The average overall latency of an MSHR miss. */
425 Stats::Formula overallAvgMshrMissLatency;
426
427 /** The average latency of an MSHR miss, per command and thread. */
428 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
429 /** The average overall latency of an MSHR miss. */
430 Stats::Formula overallAvgMshrUncacheableLatency;
431
432 /** The number of times a thread hit its MSHR cap. */
433 Stats::Vector mshr_cap_events;
434 /** The number of times software prefetches caused the MSHR to block. */
435 Stats::Vector soft_prefetch_mshr_full;
436
437 Stats::Scalar mshr_no_allocate_misses;
438
439 /**
440 * @}
441 */
442
443 /**
444 * Register stats for this object.
445 */
446 virtual void regStats();
447
448 public:
449 typedef BaseCacheParams Params;
450 BaseCache(const Params *p);
451 ~BaseCache() {}
452
453 virtual void init();
454
455 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
456 PortID idx = InvalidPortID);
457 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
458 PortID idx = InvalidPortID);
459
460 /**
461 * Query block size of a cache.
462 * @return The block size
463 */
464 unsigned
465 getBlockSize() const
466 {
467 return blkSize;
468 }
469
470
471 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
472
473
474 const AddrRangeList &getAddrRanges() const { return addrRanges; }
475
476 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
477 {
478 assert(!pkt->req->isUncacheable());
479 return allocateBufferInternal(&mshrQueue,
480 blockAlign(pkt->getAddr()), blkSize,
481 pkt, time, requestBus);
482 }
483
484 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
485 {
486 assert(pkt->isWrite() && !pkt->isRead());
487 return allocateBufferInternal(&writeBuffer,
488 pkt->getAddr(), pkt->getSize(),
489 pkt, time, requestBus);
490 }
491
492 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
493 {
494 assert(pkt->req->isUncacheable());
495 assert(pkt->isRead());
496 return allocateBufferInternal(&mshrQueue,
497 pkt->getAddr(), pkt->getSize(),
498 pkt, time, requestBus);
499 }
500
501 /**
502 * Returns true if the cache is blocked for accesses.
503 */
504 bool isBlocked() const
505 {
506 return blocked != 0;
507 }
508
509 /**
510 * Marks the access path of the cache as blocked for the given cause. This
511 * also sets the blocked flag in the slave interface.
512 * @param cause The reason for the cache blocking.
513 */
514 void setBlocked(BlockedCause cause)
515 {
516 uint8_t flag = 1 << cause;
517 if (blocked == 0) {
518 blocked_causes[cause]++;
519 blockedCycle = curCycle();
520 cpuSidePort->setBlocked();
521 }
522 blocked |= flag;
523 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
524 }
525
526 /**
527 * Marks the cache as unblocked for the given cause. This also clears the
528 * blocked flags in the appropriate interfaces.
529 * @param cause The newly unblocked cause.
530 * @warning Calling this function can cause a blocked request on the bus to
531 * access the cache. The cache must be in a state to handle that request.
532 */
533 void clearBlocked(BlockedCause cause)
534 {
535 uint8_t flag = 1 << cause;
536 blocked &= ~flag;
537 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
538 if (blocked == 0) {
539 blocked_cycles[cause] += curCycle() - blockedCycle;
540 cpuSidePort->clearBlocked();
541 }
542 }
543
544 /**
545 * Request the master bus for the given cause and time.
546 * @param cause The reason for the request.
547 * @param time The time to make the request.
548 */
549 void requestMemSideBus(RequestCause cause, Tick time)
550 {
551 memSidePort->requestBus(cause, time);
552 }
553
554 /**
555 * Clear the master bus request for the given cause.
556 * @param cause The request reason to clear.
557 */
558 void deassertMemSideBusRequest(RequestCause cause)
559 {
560 // Obsolete... we no longer signal bus requests explicitly so
561 // we can't deassert them. Leaving this in as a no-op since
562 // the prefetcher calls it to indicate that it no longer wants
563 // to request a prefetch, and someday that might be
564 // interesting again.
565 }
566
567 virtual unsigned int drain(DrainManager *dm);
568
569 virtual bool inCache(Addr addr, bool is_secure) const = 0;
570
571 virtual bool inMissQueue(Addr addr, bool is_secure) const = 0;
572
573 void incMissCount(PacketPtr pkt)
574 {
575 assert(pkt->req->masterId() < system->maxMasters());
576 misses[pkt->cmdToIndex()][pkt->req->masterId()]++;
577 pkt->req->incAccessDepth();
578 if (missCount) {
579 --missCount;
580 if (missCount == 0)
581 exitSimLoop("A cache reached the maximum miss count");
582 }
583 }
584 void incHitCount(PacketPtr pkt)
585 {
586 assert(pkt->req->masterId() < system->maxMasters());
587 hits[pkt->cmdToIndex()][pkt->req->masterId()]++;
588
589 }
590
591};
592
593#endif //__BASE_CACHE_HH__
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