3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
135 }
136
137 protected:
138
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 MasterPacketQueue &_queue) :
141 QueuedMasterPort(_name, _cache, _queue)
142 { }
143
144 /**
145 * Memory-side port always snoops.
146 *
147 * @return always true
148 */
149 virtual bool isSnooping() const { return true; }
150 };
151
152 /**
153 * A cache slave port is used for the CPU-side port of the cache,
154 * and it is basically a simple timing port that uses a transmit
155 * list for responses to the CPU (or connected master). In
156 * addition, it has the functionality to block the port for
157 * incoming requests. If blocked, the port will issue a retry once
158 * unblocked.
159 */
160 class CacheSlavePort : public QueuedSlavePort
161 {
162
163 public:
164
165 /** Do not accept any new requests. */
166 void setBlocked();
167
168 /** Return to normal operation and accept new requests. */
169 void clearBlocked();
170
171 protected:
172
173 CacheSlavePort(const std::string &_name, BaseCache *_cache,
174 const std::string &_label);
175
176 /** A normal packet queue used to store responses. */
177 SlavePacketQueue queue;
178
179 bool blocked;
180
181 bool mustSendRetry;
182
183 private:
184
185 EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent;
186
187 };
188
189 CacheSlavePort *cpuSidePort;
190 CacheMasterPort *memSidePort;
191
192 protected:
193
194 /** Miss status registers */
195 MSHRQueue mshrQueue;
196
197 /** Write/writeback buffer */
198 MSHRQueue writeBuffer;
199
200 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
201 PacketPtr pkt, Tick time, bool requestBus)
202 {
203 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
204
205 if (mq->isFull()) {
206 setBlocked((BlockedCause)mq->index);
207 }
208
209 if (requestBus) {
210 requestMemSideBus((RequestCause)mq->index, time);
211 }
212
213 return mshr;
214 }
215
216 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
217 {
218 MSHRQueue *mq = mshr->queue;
219 bool wasFull = mq->isFull();
220 mq->markInService(mshr, pkt);
221 if (wasFull && !mq->isFull()) {
222 clearBlocked((BlockedCause)mq->index);
223 }
224 }
225
226 /**
227 * Write back dirty blocks in the cache using functional accesses.
228 */
229 virtual void memWriteback() = 0;
230 /**
231 * Invalidates all blocks in the cache.
232 *
233 * @warn Dirty cache lines will not be written back to
234 * memory. Make sure to call functionalWriteback() first if you
235 * want the to write them to memory.
236 */
237 virtual void memInvalidate() = 0;
238 /**
239 * Determine if there are any dirty blocks in the cache.
240 *
241 * \return true if at least one block is dirty, false otherwise.
242 */
243 virtual bool isDirty() const = 0;
244
245 /** Block size of this cache */
246 const unsigned blkSize;
247
248 /**
249 * The latency of a hit in this device.
250 */
251 const Cycles hitLatency;
252
253 /**
254 * The latency of sending reponse to its upper level cache/core on a
255 * linefill. In most contemporary processors, the return path on a cache
256 * miss is much quicker that the hit latency. The responseLatency parameter
257 * tries to capture this latency.
258 */
259 const Cycles responseLatency;
260
261 /** The number of targets for each MSHR. */
262 const int numTarget;
263
264 /** Do we forward snoops from mem side port through to cpu side port? */
265 const bool forwardSnoops;
266
267 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
268 * never try to forward ownership and similar optimizations to the cpu
269 * side */
270 const bool isTopLevel;
271
272 /**
273 * Bit vector of the blocking reasons for the access path.
274 * @sa #BlockedCause
275 */
276 uint8_t blocked;
277
278 /** Increasing order number assigned to each incoming request. */
279 uint64_t order;
280
281 /** Stores time the cache blocked for statistics. */
282 Cycles blockedCycle;
283
284 /** Pointer to the MSHR that has no targets. */
285 MSHR *noTargetMSHR;
286
287 /** The number of misses to trigger an exit event. */
288 Counter missCount;
289
290 /**
291 * The address range to which the cache responds on the CPU side.
292 * Normally this is all possible memory addresses. */
293 const AddrRangeList addrRanges;
294
295 public:
296 /** System we are currently operating in. */
297 System *system;
298
299 // Statistics
300 /**
301 * @addtogroup CacheStatistics
302 * @{
303 */
304
305 /** Number of hits per thread for each type of command. @sa Packet::Command */
306 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
307 /** Number of hits for demand accesses. */
308 Stats::Formula demandHits;
309 /** Number of hit for all accesses. */
310 Stats::Formula overallHits;
311
312 /** Number of misses per thread for each type of command. @sa Packet::Command */
313 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
314 /** Number of misses for demand accesses. */
315 Stats::Formula demandMisses;
316 /** Number of misses for all accesses. */
317 Stats::Formula overallMisses;
318
319 /**
320 * Total number of cycles per thread/command spent waiting for a miss.
321 * Used to calculate the average miss latency.
322 */
323 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
324 /** Total number of cycles spent waiting for demand misses. */
325 Stats::Formula demandMissLatency;
326 /** Total number of cycles spent waiting for all misses. */
327 Stats::Formula overallMissLatency;
328
329 /** The number of accesses per command and thread. */
330 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
331 /** The number of demand accesses. */
332 Stats::Formula demandAccesses;
333 /** The number of overall accesses. */
334 Stats::Formula overallAccesses;
335
336 /** The miss rate per command and thread. */
337 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
338 /** The miss rate of all demand accesses. */
339 Stats::Formula demandMissRate;
340 /** The miss rate for all accesses. */
341 Stats::Formula overallMissRate;
342
343 /** The average miss latency per command and thread. */
344 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
345 /** The average miss latency for demand misses. */
346 Stats::Formula demandAvgMissLatency;
347 /** The average miss latency for all misses. */
348 Stats::Formula overallAvgMissLatency;
349
350 /** The total number of cycles blocked for each blocked cause. */
351 Stats::Vector blocked_cycles;
352 /** The number of times this cache blocked for each blocked cause. */
353 Stats::Vector blocked_causes;
354
355 /** The average number of cycles blocked for each blocked cause. */
356 Stats::Formula avg_blocked;
357
358 /** The number of fast writes (WH64) performed. */
359 Stats::Scalar fastWrites;
360
361 /** The number of cache copies performed. */
362 Stats::Scalar cacheCopies;
363
364 /** Number of blocks written back per thread. */
365 Stats::Vector writebacks;
366
367 /** Number of misses that hit in the MSHRs per command and thread. */
368 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
369 /** Demand misses that hit in the MSHRs. */
370 Stats::Formula demandMshrHits;
371 /** Total number of misses that hit in the MSHRs. */
372 Stats::Formula overallMshrHits;
373
374 /** Number of misses that miss in the MSHRs, per command and thread. */
375 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
376 /** Demand misses that miss in the MSHRs. */
377 Stats::Formula demandMshrMisses;
378 /** Total number of misses that miss in the MSHRs. */
379 Stats::Formula overallMshrMisses;
380
381 /** Number of misses that miss in the MSHRs, per command and thread. */
382 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
383 /** Total number of misses that miss in the MSHRs. */
384 Stats::Formula overallMshrUncacheable;
385
386 /** Total cycle latency of each MSHR miss, per command and thread. */
387 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
388 /** Total cycle latency of demand MSHR misses. */
389 Stats::Formula demandMshrMissLatency;
390 /** Total cycle latency of overall MSHR misses. */
391 Stats::Formula overallMshrMissLatency;
392
393 /** Total cycle latency of each MSHR miss, per command and thread. */
394 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
395 /** Total cycle latency of overall MSHR misses. */
396 Stats::Formula overallMshrUncacheableLatency;
397
398#if 0
399 /** The total number of MSHR accesses per command and thread. */
400 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
401 /** The total number of demand MSHR accesses. */
402 Stats::Formula demandMshrAccesses;
403 /** The total number of MSHR accesses. */
404 Stats::Formula overallMshrAccesses;
405#endif
406
407 /** The miss rate in the MSHRs pre command and thread. */
408 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
409 /** The demand miss rate in the MSHRs. */
410 Stats::Formula demandMshrMissRate;
411 /** The overall miss rate in the MSHRs. */
412 Stats::Formula overallMshrMissRate;
413
414 /** The average latency of an MSHR miss, per command and thread. */
415 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
416 /** The average latency of a demand MSHR miss. */
417 Stats::Formula demandAvgMshrMissLatency;
418 /** The average overall latency of an MSHR miss. */
419 Stats::Formula overallAvgMshrMissLatency;
420
421 /** The average latency of an MSHR miss, per command and thread. */
422 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
423 /** The average overall latency of an MSHR miss. */
424 Stats::Formula overallAvgMshrUncacheableLatency;
425
426 /** The number of times a thread hit its MSHR cap. */
427 Stats::Vector mshr_cap_events;
428 /** The number of times software prefetches caused the MSHR to block. */
429 Stats::Vector soft_prefetch_mshr_full;
430
431 Stats::Scalar mshr_no_allocate_misses;
432
433 /**
434 * @}
435 */
436
437 /**
438 * Register stats for this object.
439 */
440 virtual void regStats();
441
442 public:
443 typedef BaseCacheParams Params;
444 BaseCache(const Params *p);
445 ~BaseCache() {}
446
447 virtual void init();
448
449 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
450 PortID idx = InvalidPortID);
451 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
452 PortID idx = InvalidPortID);
453
454 /**
455 * Query block size of a cache.
456 * @return The block size
457 */
458 unsigned
459 getBlockSize() const
460 {
461 return blkSize;
462 }
463
464
465 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
466
467
468 const AddrRangeList &getAddrRanges() const { return addrRanges; }
469
470 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
471 {
472 assert(!pkt->req->isUncacheable());
473 return allocateBufferInternal(&mshrQueue,
474 blockAlign(pkt->getAddr()), blkSize,
475 pkt, time, requestBus);
476 }
477
478 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
479 {
480 assert(pkt->isWrite() && !pkt->isRead());
481 return allocateBufferInternal(&writeBuffer,
482 pkt->getAddr(), pkt->getSize(),
483 pkt, time, requestBus);
484 }
485
486 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
487 {
488 assert(pkt->req->isUncacheable());
489 assert(pkt->isRead());
490 return allocateBufferInternal(&mshrQueue,
491 pkt->getAddr(), pkt->getSize(),
492 pkt, time, requestBus);
493 }
494
495 /**
496 * Returns true if the cache is blocked for accesses.
497 */
498 bool isBlocked() const
499 {
500 return blocked != 0;
501 }
502
503 /**
504 * Marks the access path of the cache as blocked for the given cause. This
505 * also sets the blocked flag in the slave interface.
506 * @param cause The reason for the cache blocking.
507 */
508 void setBlocked(BlockedCause cause)
509 {
510 uint8_t flag = 1 << cause;
511 if (blocked == 0) {
512 blocked_causes[cause]++;
513 blockedCycle = curCycle();
514 cpuSidePort->setBlocked();
515 }
516 blocked |= flag;
517 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
518 }
519
520 /**
521 * Marks the cache as unblocked for the given cause. This also clears the
522 * blocked flags in the appropriate interfaces.
523 * @param cause The newly unblocked cause.
524 * @warning Calling this function can cause a blocked request on the bus to
525 * access the cache. The cache must be in a state to handle that request.
526 */
527 void clearBlocked(BlockedCause cause)
528 {
529 uint8_t flag = 1 << cause;
530 blocked &= ~flag;
531 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
532 if (blocked == 0) {
533 blocked_cycles[cause] += curCycle() - blockedCycle;
534 cpuSidePort->clearBlocked();
535 }
536 }
537
538 /**
539 * Request the master bus for the given cause and time.
540 * @param cause The reason for the request.
541 * @param time The time to make the request.
542 */
543 void requestMemSideBus(RequestCause cause, Tick time)
544 {
545 memSidePort->requestBus(cause, time);
546 }
547
548 /**
549 * Clear the master bus request for the given cause.
550 * @param cause The request reason to clear.
551 */
552 void deassertMemSideBusRequest(RequestCause cause)
553 {
554 // Obsolete... we no longer signal bus requests explicitly so
555 // we can't deassert them. Leaving this in as a no-op since
556 // the prefetcher calls it to indicate that it no longer wants
557 // to request a prefetch, and someday that might be
558 // interesting again.
559 }
560
561 virtual unsigned int drain(DrainManager *dm);
562
| 3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Erik Hallnor
41 * Steve Reinhardt
42 * Ron Dreslinski
43 */
44
45/**
46 * @file
47 * Declares a basic cache interface BaseCache.
48 */
49
50#ifndef __BASE_CACHE_HH__
51#define __BASE_CACHE_HH__
52
53#include <algorithm>
54#include <list>
55#include <string>
56#include <vector>
57
58#include "base/misc.hh"
59#include "base/statistics.hh"
60#include "base/trace.hh"
61#include "base/types.hh"
62#include "debug/Cache.hh"
63#include "debug/CachePort.hh"
64#include "mem/cache/mshr_queue.hh"
65#include "mem/mem_object.hh"
66#include "mem/packet.hh"
67#include "mem/qport.hh"
68#include "mem/request.hh"
69#include "params/BaseCache.hh"
70#include "sim/eventq.hh"
71#include "sim/full_system.hh"
72#include "sim/sim_exit.hh"
73#include "sim/system.hh"
74
75class MSHR;
76/**
77 * A basic cache interface. Implements some common functions for speed.
78 */
79class BaseCache : public MemObject
80{
81 /**
82 * Indexes to enumerate the MSHR queues.
83 */
84 enum MSHRQueueIndex {
85 MSHRQueue_MSHRs,
86 MSHRQueue_WriteBuffer
87 };
88
89 public:
90 /**
91 * Reasons for caches to be blocked.
92 */
93 enum BlockedCause {
94 Blocked_NoMSHRs = MSHRQueue_MSHRs,
95 Blocked_NoWBBuffers = MSHRQueue_WriteBuffer,
96 Blocked_NoTargets,
97 NUM_BLOCKED_CAUSES
98 };
99
100 /**
101 * Reasons for cache to request a bus.
102 */
103 enum RequestCause {
104 Request_MSHR = MSHRQueue_MSHRs,
105 Request_WB = MSHRQueue_WriteBuffer,
106 Request_PF,
107 NUM_REQUEST_CAUSES
108 };
109
110 protected:
111
112 /**
113 * A cache master port is used for the memory-side port of the
114 * cache, and in addition to the basic timing port that only sends
115 * response packets through a transmit list, it also offers the
116 * ability to schedule and send request packets (requests &
117 * writebacks). The send event is scheduled through requestBus,
118 * and the sendDeferredPacket of the timing port is modified to
119 * consider both the transmit list and the requests from the MSHR.
120 */
121 class CacheMasterPort : public QueuedMasterPort
122 {
123
124 public:
125
126 /**
127 * Schedule a send of a request packet (from the MSHR). Note
128 * that we could already have a retry or a transmit list of
129 * responses outstanding.
130 */
131 void requestBus(RequestCause cause, Tick time)
132 {
133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
134 queue.schedSendEvent(time);
135 }
136
137 protected:
138
139 CacheMasterPort(const std::string &_name, BaseCache *_cache,
140 MasterPacketQueue &_queue) :
141 QueuedMasterPort(_name, _cache, _queue)
142 { }
143
144 /**
145 * Memory-side port always snoops.
146 *
147 * @return always true
148 */
149 virtual bool isSnooping() const { return true; }
150 };
151
152 /**
153 * A cache slave port is used for the CPU-side port of the cache,
154 * and it is basically a simple timing port that uses a transmit
155 * list for responses to the CPU (or connected master). In
156 * addition, it has the functionality to block the port for
157 * incoming requests. If blocked, the port will issue a retry once
158 * unblocked.
159 */
160 class CacheSlavePort : public QueuedSlavePort
161 {
162
163 public:
164
165 /** Do not accept any new requests. */
166 void setBlocked();
167
168 /** Return to normal operation and accept new requests. */
169 void clearBlocked();
170
171 protected:
172
173 CacheSlavePort(const std::string &_name, BaseCache *_cache,
174 const std::string &_label);
175
176 /** A normal packet queue used to store responses. */
177 SlavePacketQueue queue;
178
179 bool blocked;
180
181 bool mustSendRetry;
182
183 private:
184
185 EventWrapper<SlavePort, &SlavePort::sendRetry> sendRetryEvent;
186
187 };
188
189 CacheSlavePort *cpuSidePort;
190 CacheMasterPort *memSidePort;
191
192 protected:
193
194 /** Miss status registers */
195 MSHRQueue mshrQueue;
196
197 /** Write/writeback buffer */
198 MSHRQueue writeBuffer;
199
200 MSHR *allocateBufferInternal(MSHRQueue *mq, Addr addr, int size,
201 PacketPtr pkt, Tick time, bool requestBus)
202 {
203 MSHR *mshr = mq->allocate(addr, size, pkt, time, order++);
204
205 if (mq->isFull()) {
206 setBlocked((BlockedCause)mq->index);
207 }
208
209 if (requestBus) {
210 requestMemSideBus((RequestCause)mq->index, time);
211 }
212
213 return mshr;
214 }
215
216 void markInServiceInternal(MSHR *mshr, PacketPtr pkt)
217 {
218 MSHRQueue *mq = mshr->queue;
219 bool wasFull = mq->isFull();
220 mq->markInService(mshr, pkt);
221 if (wasFull && !mq->isFull()) {
222 clearBlocked((BlockedCause)mq->index);
223 }
224 }
225
226 /**
227 * Write back dirty blocks in the cache using functional accesses.
228 */
229 virtual void memWriteback() = 0;
230 /**
231 * Invalidates all blocks in the cache.
232 *
233 * @warn Dirty cache lines will not be written back to
234 * memory. Make sure to call functionalWriteback() first if you
235 * want the to write them to memory.
236 */
237 virtual void memInvalidate() = 0;
238 /**
239 * Determine if there are any dirty blocks in the cache.
240 *
241 * \return true if at least one block is dirty, false otherwise.
242 */
243 virtual bool isDirty() const = 0;
244
245 /** Block size of this cache */
246 const unsigned blkSize;
247
248 /**
249 * The latency of a hit in this device.
250 */
251 const Cycles hitLatency;
252
253 /**
254 * The latency of sending reponse to its upper level cache/core on a
255 * linefill. In most contemporary processors, the return path on a cache
256 * miss is much quicker that the hit latency. The responseLatency parameter
257 * tries to capture this latency.
258 */
259 const Cycles responseLatency;
260
261 /** The number of targets for each MSHR. */
262 const int numTarget;
263
264 /** Do we forward snoops from mem side port through to cpu side port? */
265 const bool forwardSnoops;
266
267 /** Is this cache a toplevel cache (e.g. L1, I/O cache). If so we should
268 * never try to forward ownership and similar optimizations to the cpu
269 * side */
270 const bool isTopLevel;
271
272 /**
273 * Bit vector of the blocking reasons for the access path.
274 * @sa #BlockedCause
275 */
276 uint8_t blocked;
277
278 /** Increasing order number assigned to each incoming request. */
279 uint64_t order;
280
281 /** Stores time the cache blocked for statistics. */
282 Cycles blockedCycle;
283
284 /** Pointer to the MSHR that has no targets. */
285 MSHR *noTargetMSHR;
286
287 /** The number of misses to trigger an exit event. */
288 Counter missCount;
289
290 /**
291 * The address range to which the cache responds on the CPU side.
292 * Normally this is all possible memory addresses. */
293 const AddrRangeList addrRanges;
294
295 public:
296 /** System we are currently operating in. */
297 System *system;
298
299 // Statistics
300 /**
301 * @addtogroup CacheStatistics
302 * @{
303 */
304
305 /** Number of hits per thread for each type of command. @sa Packet::Command */
306 Stats::Vector hits[MemCmd::NUM_MEM_CMDS];
307 /** Number of hits for demand accesses. */
308 Stats::Formula demandHits;
309 /** Number of hit for all accesses. */
310 Stats::Formula overallHits;
311
312 /** Number of misses per thread for each type of command. @sa Packet::Command */
313 Stats::Vector misses[MemCmd::NUM_MEM_CMDS];
314 /** Number of misses for demand accesses. */
315 Stats::Formula demandMisses;
316 /** Number of misses for all accesses. */
317 Stats::Formula overallMisses;
318
319 /**
320 * Total number of cycles per thread/command spent waiting for a miss.
321 * Used to calculate the average miss latency.
322 */
323 Stats::Vector missLatency[MemCmd::NUM_MEM_CMDS];
324 /** Total number of cycles spent waiting for demand misses. */
325 Stats::Formula demandMissLatency;
326 /** Total number of cycles spent waiting for all misses. */
327 Stats::Formula overallMissLatency;
328
329 /** The number of accesses per command and thread. */
330 Stats::Formula accesses[MemCmd::NUM_MEM_CMDS];
331 /** The number of demand accesses. */
332 Stats::Formula demandAccesses;
333 /** The number of overall accesses. */
334 Stats::Formula overallAccesses;
335
336 /** The miss rate per command and thread. */
337 Stats::Formula missRate[MemCmd::NUM_MEM_CMDS];
338 /** The miss rate of all demand accesses. */
339 Stats::Formula demandMissRate;
340 /** The miss rate for all accesses. */
341 Stats::Formula overallMissRate;
342
343 /** The average miss latency per command and thread. */
344 Stats::Formula avgMissLatency[MemCmd::NUM_MEM_CMDS];
345 /** The average miss latency for demand misses. */
346 Stats::Formula demandAvgMissLatency;
347 /** The average miss latency for all misses. */
348 Stats::Formula overallAvgMissLatency;
349
350 /** The total number of cycles blocked for each blocked cause. */
351 Stats::Vector blocked_cycles;
352 /** The number of times this cache blocked for each blocked cause. */
353 Stats::Vector blocked_causes;
354
355 /** The average number of cycles blocked for each blocked cause. */
356 Stats::Formula avg_blocked;
357
358 /** The number of fast writes (WH64) performed. */
359 Stats::Scalar fastWrites;
360
361 /** The number of cache copies performed. */
362 Stats::Scalar cacheCopies;
363
364 /** Number of blocks written back per thread. */
365 Stats::Vector writebacks;
366
367 /** Number of misses that hit in the MSHRs per command and thread. */
368 Stats::Vector mshr_hits[MemCmd::NUM_MEM_CMDS];
369 /** Demand misses that hit in the MSHRs. */
370 Stats::Formula demandMshrHits;
371 /** Total number of misses that hit in the MSHRs. */
372 Stats::Formula overallMshrHits;
373
374 /** Number of misses that miss in the MSHRs, per command and thread. */
375 Stats::Vector mshr_misses[MemCmd::NUM_MEM_CMDS];
376 /** Demand misses that miss in the MSHRs. */
377 Stats::Formula demandMshrMisses;
378 /** Total number of misses that miss in the MSHRs. */
379 Stats::Formula overallMshrMisses;
380
381 /** Number of misses that miss in the MSHRs, per command and thread. */
382 Stats::Vector mshr_uncacheable[MemCmd::NUM_MEM_CMDS];
383 /** Total number of misses that miss in the MSHRs. */
384 Stats::Formula overallMshrUncacheable;
385
386 /** Total cycle latency of each MSHR miss, per command and thread. */
387 Stats::Vector mshr_miss_latency[MemCmd::NUM_MEM_CMDS];
388 /** Total cycle latency of demand MSHR misses. */
389 Stats::Formula demandMshrMissLatency;
390 /** Total cycle latency of overall MSHR misses. */
391 Stats::Formula overallMshrMissLatency;
392
393 /** Total cycle latency of each MSHR miss, per command and thread. */
394 Stats::Vector mshr_uncacheable_lat[MemCmd::NUM_MEM_CMDS];
395 /** Total cycle latency of overall MSHR misses. */
396 Stats::Formula overallMshrUncacheableLatency;
397
398#if 0
399 /** The total number of MSHR accesses per command and thread. */
400 Stats::Formula mshrAccesses[MemCmd::NUM_MEM_CMDS];
401 /** The total number of demand MSHR accesses. */
402 Stats::Formula demandMshrAccesses;
403 /** The total number of MSHR accesses. */
404 Stats::Formula overallMshrAccesses;
405#endif
406
407 /** The miss rate in the MSHRs pre command and thread. */
408 Stats::Formula mshrMissRate[MemCmd::NUM_MEM_CMDS];
409 /** The demand miss rate in the MSHRs. */
410 Stats::Formula demandMshrMissRate;
411 /** The overall miss rate in the MSHRs. */
412 Stats::Formula overallMshrMissRate;
413
414 /** The average latency of an MSHR miss, per command and thread. */
415 Stats::Formula avgMshrMissLatency[MemCmd::NUM_MEM_CMDS];
416 /** The average latency of a demand MSHR miss. */
417 Stats::Formula demandAvgMshrMissLatency;
418 /** The average overall latency of an MSHR miss. */
419 Stats::Formula overallAvgMshrMissLatency;
420
421 /** The average latency of an MSHR miss, per command and thread. */
422 Stats::Formula avgMshrUncacheableLatency[MemCmd::NUM_MEM_CMDS];
423 /** The average overall latency of an MSHR miss. */
424 Stats::Formula overallAvgMshrUncacheableLatency;
425
426 /** The number of times a thread hit its MSHR cap. */
427 Stats::Vector mshr_cap_events;
428 /** The number of times software prefetches caused the MSHR to block. */
429 Stats::Vector soft_prefetch_mshr_full;
430
431 Stats::Scalar mshr_no_allocate_misses;
432
433 /**
434 * @}
435 */
436
437 /**
438 * Register stats for this object.
439 */
440 virtual void regStats();
441
442 public:
443 typedef BaseCacheParams Params;
444 BaseCache(const Params *p);
445 ~BaseCache() {}
446
447 virtual void init();
448
449 virtual BaseMasterPort &getMasterPort(const std::string &if_name,
450 PortID idx = InvalidPortID);
451 virtual BaseSlavePort &getSlavePort(const std::string &if_name,
452 PortID idx = InvalidPortID);
453
454 /**
455 * Query block size of a cache.
456 * @return The block size
457 */
458 unsigned
459 getBlockSize() const
460 {
461 return blkSize;
462 }
463
464
465 Addr blockAlign(Addr addr) const { return (addr & ~(Addr(blkSize - 1))); }
466
467
468 const AddrRangeList &getAddrRanges() const { return addrRanges; }
469
470 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus)
471 {
472 assert(!pkt->req->isUncacheable());
473 return allocateBufferInternal(&mshrQueue,
474 blockAlign(pkt->getAddr()), blkSize,
475 pkt, time, requestBus);
476 }
477
478 MSHR *allocateWriteBuffer(PacketPtr pkt, Tick time, bool requestBus)
479 {
480 assert(pkt->isWrite() && !pkt->isRead());
481 return allocateBufferInternal(&writeBuffer,
482 pkt->getAddr(), pkt->getSize(),
483 pkt, time, requestBus);
484 }
485
486 MSHR *allocateUncachedReadBuffer(PacketPtr pkt, Tick time, bool requestBus)
487 {
488 assert(pkt->req->isUncacheable());
489 assert(pkt->isRead());
490 return allocateBufferInternal(&mshrQueue,
491 pkt->getAddr(), pkt->getSize(),
492 pkt, time, requestBus);
493 }
494
495 /**
496 * Returns true if the cache is blocked for accesses.
497 */
498 bool isBlocked() const
499 {
500 return blocked != 0;
501 }
502
503 /**
504 * Marks the access path of the cache as blocked for the given cause. This
505 * also sets the blocked flag in the slave interface.
506 * @param cause The reason for the cache blocking.
507 */
508 void setBlocked(BlockedCause cause)
509 {
510 uint8_t flag = 1 << cause;
511 if (blocked == 0) {
512 blocked_causes[cause]++;
513 blockedCycle = curCycle();
514 cpuSidePort->setBlocked();
515 }
516 blocked |= flag;
517 DPRINTF(Cache,"Blocking for cause %d, mask=%d\n", cause, blocked);
518 }
519
520 /**
521 * Marks the cache as unblocked for the given cause. This also clears the
522 * blocked flags in the appropriate interfaces.
523 * @param cause The newly unblocked cause.
524 * @warning Calling this function can cause a blocked request on the bus to
525 * access the cache. The cache must be in a state to handle that request.
526 */
527 void clearBlocked(BlockedCause cause)
528 {
529 uint8_t flag = 1 << cause;
530 blocked &= ~flag;
531 DPRINTF(Cache,"Unblocking for cause %d, mask=%d\n", cause, blocked);
532 if (blocked == 0) {
533 blocked_cycles[cause] += curCycle() - blockedCycle;
534 cpuSidePort->clearBlocked();
535 }
536 }
537
538 /**
539 * Request the master bus for the given cause and time.
540 * @param cause The reason for the request.
541 * @param time The time to make the request.
542 */
543 void requestMemSideBus(RequestCause cause, Tick time)
544 {
545 memSidePort->requestBus(cause, time);
546 }
547
548 /**
549 * Clear the master bus request for the given cause.
550 * @param cause The request reason to clear.
551 */
552 void deassertMemSideBusRequest(RequestCause cause)
553 {
554 // Obsolete... we no longer signal bus requests explicitly so
555 // we can't deassert them. Leaving this in as a no-op since
556 // the prefetcher calls it to indicate that it no longer wants
557 // to request a prefetch, and someday that might be
558 // interesting again.
559 }
560
561 virtual unsigned int drain(DrainManager *dm);
562
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