base.hh (5999:3cf8e71257e0) | base.hh (6122:9af6fb59752f) |
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1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 86 unchanged lines hidden (view full) --- 95 96 class CachePort : public SimpleTimingPort 97 { 98 public: 99 BaseCache *cache; 100 101 protected: 102 CachePort(const std::string &_name, BaseCache *_cache, | 1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 86 unchanged lines hidden (view full) --- 95 96 class CachePort : public SimpleTimingPort 97 { 98 public: 99 BaseCache *cache; 100 101 protected: 102 CachePort(const std::string &_name, BaseCache *_cache, |
103 const std::string &_label, 104 std::vector<Range<Addr> > filter_ranges); | 103 const std::string &_label); |
105 106 virtual void recvStatusChange(Status status); 107 108 virtual int deviceBlockSize(); 109 110 bool recvRetryCommon(); 111 112 typedef EventWrapper<Port, &Port::sendRetry> --- 11 unchanged lines hidden (view full) --- 124 bool checkFunctional(PacketPtr pkt); 125 126 CachePort *otherPort; 127 128 bool blocked; 129 130 bool mustSendRetry; 131 | 104 105 virtual void recvStatusChange(Status status); 106 107 virtual int deviceBlockSize(); 108 109 bool recvRetryCommon(); 110 111 typedef EventWrapper<Port, &Port::sendRetry> --- 11 unchanged lines hidden (view full) --- 123 bool checkFunctional(PacketPtr pkt); 124 125 CachePort *otherPort; 126 127 bool blocked; 128 129 bool mustSendRetry; 130 |
132 /** filter ranges */ 133 std::vector<Range<Addr> > filterRanges; 134 | |
135 void requestBus(RequestCause cause, Tick time) 136 { 137 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 138 if (!waitingOnRetry) { 139 schedSendEvent(time); 140 } 141 } 142 --- 46 unchanged lines hidden (view full) --- 189 /** 190 * The latency of a hit in this device. 191 */ 192 int hitLatency; 193 194 /** The number of targets for each MSHR. */ 195 const int numTarget; 196 | 131 void requestBus(RequestCause cause, Tick time) 132 { 133 DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause); 134 if (!waitingOnRetry) { 135 schedSendEvent(time); 136 } 137 } 138 --- 46 unchanged lines hidden (view full) --- 185 /** 186 * The latency of a hit in this device. 187 */ 188 int hitLatency; 189 190 /** The number of targets for each MSHR. */ 191 const int numTarget; 192 |
197 /** Increasing order number assigned to each incoming request. */ 198 uint64_t order; | 193 /** Do we forward snoops from mem side port through to cpu side port? */ 194 bool forwardSnoops; |
199 200 /** 201 * Bit vector of the blocking reasons for the access path. 202 * @sa #BlockedCause 203 */ 204 uint8_t blocked; 205 | 195 196 /** 197 * Bit vector of the blocking reasons for the access path. 198 * @sa #BlockedCause 199 */ 200 uint8_t blocked; 201 |
202 /** Increasing order number assigned to each incoming request. */ 203 uint64_t order; 204 |
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206 /** Stores time the cache blocked for statistics. */ 207 Tick blockedCycle; 208 209 /** Pointer to the MSHR that has no targets. */ 210 MSHR *noTargetMSHR; 211 212 /** The number of misses to trigger an exit event. */ 213 Counter missCount; 214 215 /** The drain event. */ 216 Event *drainEvent; 217 | 205 /** Stores time the cache blocked for statistics. */ 206 Tick blockedCycle; 207 208 /** Pointer to the MSHR that has no targets. */ 209 MSHR *noTargetMSHR; 210 211 /** The number of misses to trigger an exit event. */ 212 Counter missCount; 213 214 /** The drain event. */ 215 Event *drainEvent; 216 |
217 /** 218 * The address range to which the cache responds on the CPU side. 219 * Normally this is all possible memory addresses. */ 220 Range<Addr> addrRange; 221 |
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218 public: 219 // Statistics 220 /** 221 * @addtogroup CacheStatistics 222 * @{ 223 */ 224 225 /** Number of hits per thread for each type of command. @sa Packet::Command */ --- 146 unchanged lines hidden (view full) --- 372 { 373 return blkSize; 374 } 375 376 377 Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); } 378 379 | 222 public: 223 // Statistics 224 /** 225 * @addtogroup CacheStatistics 226 * @{ 227 */ 228 229 /** Number of hits per thread for each type of command. @sa Packet::Command */ --- 146 unchanged lines hidden (view full) --- 376 { 377 return blkSize; 378 } 379 380 381 Addr blockAlign(Addr addr) const { return (addr & ~(blkSize - 1)); } 382 383 |
384 const Range<Addr> &getAddrRange() const { return addrRange; } 385 |
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380 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 381 { 382 assert(!pkt->req->isUncacheable()); 383 return allocateBufferInternal(&mshrQueue, 384 blockAlign(pkt->getAddr()), blkSize, 385 pkt, time, requestBus); 386 } 387 --- 103 unchanged lines hidden --- | 386 MSHR *allocateMissBuffer(PacketPtr pkt, Tick time, bool requestBus) 387 { 388 assert(!pkt->req->isUncacheable()); 389 return allocateBufferInternal(&mshrQueue, 390 blockAlign(pkt->getAddr()), blkSize, 391 pkt, time, requestBus); 392 } 393 --- 103 unchanged lines hidden --- |